diff --git a/CMakeLists.txt b/CMakeLists.txt index 39b1242..c31ab1b 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -37,6 +37,7 @@ option(ENABLE_JLINK "enable JLink cable (requires libUSB)" ${ option(ENABLE_DFU "enable DFU support (requires libUSB)" ${ENABLE_CABLE_ALL}) option(ENABLE_FTDI_BASED_CABLE "enable cables based on FTDI (requires libFTDI" ${ENABLE_CABLE_ALL}) option(ENABLE_GOWIN_GWU2X "enable Gowin GWU2X interface" ${ENABLE_CABLE_ALL}) +option(ENABLE_SVF_JTAG "enable SVF support" ${ENABLE_CABLE_ALL}) option(ENABLE_USB_BLASTERI "enable Altera USB Blaster I support" ${ENABLE_CABLE_ALL}) option(ENABLE_USB_BLASTERII "enable Altera USB Blaster II support" ${ENABLE_CABLE_ALL}) @@ -54,6 +55,23 @@ else() set(ENABLE_XILINX_VIRTUAL_CABLE OFF) endif() +#################################################################################################### +# VENDORS Options +#################################################################################################### + +# set all vendor on by default +option(ENABLE_VENDORS_ALL "Enable all vendors support" ON) + +option(ENABLE_ALTERA_SUPPORT "enable Altera FPGAs Support" ${ENABLE_VENDORS_ALL}) +option(ENABLE_ANLOGIC_SUPPORT "enable Anlogic FPGAs Support" ${ENABLE_VENDORS_ALL}) +option(ENABLE_COLOGNECHIP_SUPPORT "enable CologneChip FPGAs Support (requires libftdi)" ${ENABLE_VENDORS_ALL}) +option(ENABLE_EFINIX_SUPPORT "enable Efinix FPGAs Support (requires libftdi)" ${ENABLE_VENDORS_ALL}) +option(ENABLE_GOWIN_SUPPORT "enable Gowin FPGAs Support" ${ENABLE_VENDORS_ALL}) +option(ENABLE_ICE40_SUPPORT "enable Ice40 FPGAs Support (requires libftdi)" ${ENABLE_VENDORS_ALL}) +option(ENABLE_LATTICE_SUPPORT "enable Lattice FPGAs Support" ${ENABLE_VENDORS_ALL}) +option(ENABLE_LATTICESSPI_SUPPORT "enable Lattice FPGAs Support (SSPI / requires libftdi)" ${ENABLE_VENDORS_ALL}) +option(ENABLE_XILINX_SUPPORT "enable Xilinx FPGAs Support" ${ENABLE_VENDORS_ALL}) + #################################################################################################### # Variables #################################################################################################### @@ -114,11 +132,23 @@ add_definitions(-DISE_DIR=\"${ISE_PATH}\") # Dependencies check/search #################################################################################################### +if (USE_LIBFTDI) + # Try to find the LibFTDI1 with cmake + find_package(LibFTDI1 QUIET) +endif() + if (USE_PKGCONFIG) find_package(PkgConfig REQUIRED) + # Backward compat when the libftdi is not found + # by using cmake if (USE_LIBFTDI) - pkg_check_modules(LIBFTDI REQUIRED libftdi1) + if (NOT LIBFTDI_FOUND) + pkg_check_modules(LIBFTDI REQUIRED libftdi1) + string(REPLACE "." ";" VERSION_LIST ${LIBFTDI_VERSION}) + list(GET VERSION_LIST 0 LIBFTDI_VERSION_MAJOR) + list(GET VERSION_LIST 1 LIBFTDI_VERSION_MINOR) + endif() else() set(LIBFTDI_LIBRARY_DIRS "") set(LIBFTDI_INCLUDE_DIRS "") @@ -134,7 +164,7 @@ if (USE_PKGCONFIG) endif(USE_LIBUSB) if(ENABLE_CMSISDAP) - pkg_check_modules(HIDAPI hidapi-libusb) + pkg_check_modules(HIDAPI hidapi-libusb) # if libusb not found try with hidraw if (NOT HIDAPI_FOUND) pkg_check_modules(HIDAPI hidapi-hidraw) @@ -143,6 +173,7 @@ if (USE_PKGCONFIG) pkg_check_modules(HIDAPI hidapi) endif() endif() + # zlib support (gzip) pkg_check_modules(ZLIB zlib) if (NOT ZLIB_FOUND) @@ -205,47 +236,33 @@ set(OPENFPGALOADER_HEADERS # =========================== # Parsers classes # =========================== -list(APPEND OPENFPGALOADER_SOURCE - src/anlogicBitParser.cpp - src/bitparser.cpp - src/fsparser.cpp - src/ihexParser.cpp - src/mcsParser.cpp - src/pofParser.cpp - src/rawParser.cpp - src/xilinxMapParser.cpp -) +list(APPEND OPENFPGALOADER_SOURCE src/rawParser.cpp) +list(APPEND OPENFPGALOADER_HEADERS src/rawParser.hpp) -list(APPEND OPENFPGALOADER_HEADERS - src/anlogicBitParser.hpp - src/bitparser.hpp - src/fsparser.hpp - src/ihexParser.hpp - src/mcsParser.hpp - src/pofParser.hpp - src/rawParser.hpp - src/xilinxMapParser.hpp -) +if (${ENABLE_LATTICE_SUPPORT} OR ${ENABLE_XILINX_SUPPORT}) + list(APPEND OPENFPGALOADER_SOURCE + src/jedParser.cpp + src/mcsParser.cpp + ) + + list(APPEND OPENFPGALOADER_HEADERS + src/jedParser.hpp + src/mcsParser.hpp + ) +endif() # =========================== # To be sorted # =========================== list(APPEND OPENFPGALOADER_SOURCE - src/anlogic.cpp src/bpiFlash.cpp src/spiFlash.cpp src/spiInterface.cpp src/epcq.cpp - src/svf_jtag.cpp src/jtag.cpp - src/gowin.cpp - src/altera.cpp - src/xilinx.cpp ) list(APPEND OPENFPGALOADER_HEADERS - src/altera.hpp - src/anlogic.hpp src/bpiFlash.hpp src/jtag.hpp src/jtagInterface.hpp @@ -253,9 +270,6 @@ list(APPEND OPENFPGALOADER_HEADERS src/spiFlashdb.hpp src/epcq.hpp src/spiInterface.hpp - src/svf_jtag.hpp - src/gowin.hpp - src/xilinx.hpp ) # FTDI Based cables @@ -279,52 +293,148 @@ if (${USE_LIBFTDI}) ) # CologneChip Drivers / Files parsers. - list(APPEND OPENFPGALOADER_SOURCE - src/colognechip.cpp - src/colognechipCfgParser.cpp - ) + if (ENABLE_COLOGNECHIP_SUPPORT) + list(APPEND OPENFPGALOADER_SOURCE + src/colognechip.cpp + src/colognechipCfgParser.cpp + ) - list(APPEND OPENFPGALOADER_HEADERS - src/colognechip.hpp - src/colognechipCfgParser.hpp - ) + list(APPEND OPENFPGALOADER_HEADERS + src/colognechip.hpp + src/colognechipCfgParser.hpp + ) + add_definitions(-DENABLE_COLOGNECHIP_SUPPORT=1) + message("CologneChip support enabled") + else() + message("CologneChip support disabled") + endif(ENABLE_COLOGNECHIP_SUPPORT) # Efinix Drivers / Files parsers. - list(APPEND OPENFPGALOADER_SOURCE - src/efinix.cpp - src/efinixHexParser.cpp - ) + if (ENABLE_EFINIX_SUPPORT) + list(APPEND OPENFPGALOADER_SOURCE + src/efinix.cpp + src/efinixHexParser.cpp + ) - list(APPEND OPENFPGALOADER_HEADERS - src/efinix.hpp - src/efinixHexParser.hpp - ) + list(APPEND OPENFPGALOADER_HEADERS + src/efinix.hpp + src/efinixHexParser.hpp + ) + add_definitions(-DENABLE_EFINIX_SUPPORT=1) + message("Efinix support enabled") + else() + message("Efinix support disabled") + endif(ENABLE_EFINIX_SUPPORT) - # Lattice Drivers / Files parsers. - list(APPEND OPENFPGALOADER_SOURCE - src/ice40.cpp - src/latticeSSPI.cpp - ) - list(APPEND OPENFPGALOADER_HEADERS - src/ice40.hpp - src/latticeSSPI.hpp - ) + # ICE40 Driver. + if (ENABLE_ICE40_SUPPORT) + list(APPEND OPENFPGALOADER_SOURCE src/ice40.cpp) + list(APPEND OPENFPGALOADER_HEADERS src/ice40.hpp) + add_definitions(-DENABLE_ICE40_SUPPORT=1) + message("ICE40 support enabled") + else() + message("ICE40 support disabled") + endif(ENABLE_ICE40_SUPPORT) + + # Lattice SSPI Driver. + if (ENABLE_LATTICESSPI_SUPPORT) + list(APPEND OPENFPGALOADER_SOURCE src/latticeSSPI.cpp) + list(APPEND OPENFPGALOADER_HEADERS src/latticeSSPI.hpp) + add_definitions(-DENABLE_LATTICESSPI_SUPPORT=1) + message("Lattice SSPI support enabled") + else() + message("Lattice SSPI support disabled") + endif(ENABLE_LATTICESSPI_SUPPORT) endif() -# Lattice Drivers / Files parsers. -list(APPEND OPENFPGALOADER_SOURCE - src/lattice.cpp - src/feaparser.cpp - src/jedParser.cpp - src/latticeBitParser.cpp -) +# Altera Drivers / Files parsers. +if (ENABLE_ALTERA_SUPPORT) + list(APPEND OPENFPGALOADER_SOURCE + src/altera.cpp + src/pofParser.cpp + ) -list(APPEND OPENFPGALOADER_HEADERS - src/lattice.hpp - src/jedParser.hpp - src/feaparser.hpp - src/latticeBitParser.hpp -) + list(APPEND OPENFPGALOADER_HEADERS + src/altera.hpp + src/pofParser.hpp + ) + add_definitions(-DENABLE_ALTERA_SUPPORT=1) + message("Altera support enabled") +else() + message("Altera support disabled") +endif(ENABLE_ALTERA_SUPPORT) + +# Anlogic Drivers / Files parsers. +if (ENABLE_ANLOGIC_SUPPORT) + list(APPEND OPENFPGALOADER_SOURCE + src/anlogic.cpp + src/anlogicBitParser.cpp + ) + + list(APPEND OPENFPGALOADER_HEADERS + src/anlogic.hpp + src/anlogicBitParser.hpp + ) + add_definitions(-DENABLE_ANLOGIC_SUPPORT=1) + message("Anlogic support enabled") +else() + message("Anlogic support disabled") +endif(ENABLE_ANLOGIC_SUPPORT) + +# Gowin Drivers / Files parsers. +if (ENABLE_GOWIN_SUPPORT) + list(APPEND OPENFPGALOADER_SOURCE + src/gowin.cpp + src/fsparser.cpp + ) + + list(APPEND OPENFPGALOADER_HEADERS + src/gowin.hpp + src/fsparser.hpp + ) + add_definitions(-DENABLE_GOWIN_SUPPORT=1) + message("Gowin support enabled") +else() + message("Gowin support disabled") +endif(ENABLE_GOWIN_SUPPORT) + +# Xilinx Drivers / Files parsers. +if (ENABLE_XILINX_SUPPORT) + list(APPEND OPENFPGALOADER_SOURCE + src/bitparser.cpp + src/xilinx.cpp + src/xilinxMapParser.cpp + ) + + list(APPEND OPENFPGALOADER_HEADERS + src/bitparser.hpp + src/xilinx.hpp + src/xilinxMapParser.hpp + ) + add_definitions(-DENABLE_XILINX_SUPPORT=1) + message("Xilinx support enabled") +else() + message("Xilinx support disabled") +endif(ENABLE_XILINX_SUPPORT) + +# Lattice Drivers / Files parsers. +if (ENABLE_LATTICE_SUPPORT) + list(APPEND OPENFPGALOADER_SOURCE + src/lattice.cpp + src/feaparser.cpp + src/latticeBitParser.cpp + ) + + list(APPEND OPENFPGALOADER_HEADERS + src/lattice.hpp + src/feaparser.hpp + src/latticeBitParser.hpp + ) + add_definitions(-DENABLE_LATTICE_SUPPORT=1) + message("Lattice support enabled") +else() + message("Lattice support disabled") +endif(ENABLE_LATTICE_SUPPORT) # Cables select @@ -395,6 +505,13 @@ list (APPEND OPENFPGALOADER_SOURCE src/remoteBitbang_client.cpp) list (APPEND OPENFPGALOADER_HEADERS src/remoteBitbang_client.hpp) endif() +# SVF JTAG file type support +if (ENABLE_SVF_JTAG) +list (APPEND OPENFPGALOADER_SOURCE src/svf_jtag.cpp) +list (APPEND OPENFPGALOADER_HEADERS src/svf_jtag.hpp) +add_definitions(-DENABLE_SVF_JTAG) +endif() + # Xilinx Virtual Cable if (ENABLE_XILINX_VIRTUAL_CABLE) list (APPEND OPENFPGALOADER_SOURCE src/xvc_client.cpp src/xvc_server.cpp) @@ -437,8 +554,8 @@ list(APPEND OPENFPGALOADER_HEADERS src/libusb_ll.hpp) endif() if (USE_FX2_LL) -list(APPEND OPENFPGALOADER_SOURCE src/fx2_ll.cpp) -list(APPEND OPENFPGALOADER_HEADERS src/fx2_ll.hpp) +list(APPEND OPENFPGALOADER_SOURCE src/fx2_ll.cpp src/ihexParser.cpp) +list(APPEND OPENFPGALOADER_HEADERS src/fx2_ll.hpp src/ihexParser.hpp) endif() add_executable(openFPGALoader @@ -606,9 +723,6 @@ endif() if (USE_LIBFTDI) # libftdi < 1.4 as no usb_addr # libftdi >= 1.5 as purge_buffer obsolete - string(REPLACE "." ";" VERSION_LIST ${LIBFTDI_VERSION}) - list(GET VERSION_LIST 0 LIBFTDI_VERSION_MAJOR) - list(GET VERSION_LIST 1 LIBFTDI_VERSION_MINOR) math(EXPR FTDI_VAL "${LIBFTDI_VERSION_MAJOR} * 100 + ${LIBFTDI_VERSION_MINOR}") add_definitions(-DFTDI_VERSION=${FTDI_VAL}) endif() diff --git a/spiOverJtag/Makefile b/spiOverJtag/Makefile index 344e714..91fd1de 100644 --- a/spiOverJtag/Makefile +++ b/spiOverJtag/Makefile @@ -17,7 +17,7 @@ XILINX_PARTS := xc3s500evq100 \ xcau15p-ffvb676 XILINX_BIT_FILES := $(addsuffix .bit.gz,$(addprefix spiOverJtag_, $(XILINX_PARTS))) -ALTERA_PARTS := 10cl025256 10cl016484 10cl055484 \ +ALTERA_PARTS := 10cl025256 10cl016484 10cl055484 10cl006144 \ ep4ce622 ep4ce1017 ep4ce2217 ep4ce1523 ep4ce11523 ep4cgx15027 5ce215 5ce223 5ce423 5ce523 5ce927 5sgsd5 ALTERA_BIT_FILES := $(addsuffix .rbf.gz, $(addprefix spiOverJtag_, $(ALTERA_PARTS))) diff --git a/spiOverJtag/altclkctrl_inst.v b/spiOverJtag/altclkctrl_inst.v new file mode 100644 index 0000000..bbe4b19 --- /dev/null +++ b/spiOverJtag/altclkctrl_inst.v @@ -0,0 +1,11 @@ +module altclkctrl_inst ( + input wire inclk, + input wire ena, + output wire outclk +); +altclkctrl u ( + .inclk(inclk), + .ena(ena), + .outclk(outclk) +); +endmodule diff --git a/spiOverJtag/build.py b/spiOverJtag/build.py index 7233563..8ae4ec3 100755 --- a/spiOverJtag/build.py +++ b/spiOverJtag/build.py @@ -222,6 +222,7 @@ else: "10cl016484" : "10CL016YU484C8G", "10cl025256" : "10CL025YU256C8G", "10cl055484" : "10CL055YU484C8G", + "10cl006144" : "10CL006YE144C8G", "ep4cgx15027": "EP4CGX150DF27I7", "ep4ce11523" : "EP4CE115F23C7", "ep4ce2217" : "EP4CE22F17C6", @@ -238,6 +239,8 @@ else: "5sgsd5" : "5SGSMD5K2F40I3"}[part] files.append({'name': currDir + 'altera_spiOverJtag.v', 'file_type': 'verilogSource'}) + files.append({'name': currDir + 'altclkctrl_inst.v', + 'file_type': 'verilogSource'}) files.append({'name': currDir + 'altera_spiOverJtag.sdc', 'file_type': 'SDC'}) tool_options = {'device': full_part, 'family':family} diff --git a/spiOverJtag/spiOverJtag_10cl006144.rbf.gz b/spiOverJtag/spiOverJtag_10cl006144.rbf.gz new file mode 100644 index 0000000..72b3170 Binary files /dev/null and b/spiOverJtag/spiOverJtag_10cl006144.rbf.gz differ diff --git a/src/ch347jtag.cpp b/src/ch347jtag.cpp index ff2f7ab..8f5c14f 100644 --- a/src/ch347jtag.cpp +++ b/src/ch347jtag.cpp @@ -249,14 +249,17 @@ int CH347Jtag::_setClkFreq(uint32_t clkHZ) uint32_t *ptr = _is_largerPack ? speed_clock_larger_pack : speed_clock_standard_pack; int size = (_is_largerPack?sizeof(speed_clock_larger_pack):sizeof(speed_clock_standard_pack)) / sizeof(uint32_t); for (int i = 0; i < size; ++i) { - if (clkHZ > ptr[i] && clkHZ <= ptr[i+1]){ - setClk_index = i + 1; - } + if (clkHZ >= ptr[i] ){ + setClk_index = i; + } else { + break; + } } if (setClk(setClk_index)) { printError("failed to set clock rate"); return 0; } + _clkHZ = ptr[setClk_index]; char mess[256]; snprintf(mess, 256, "JTAG TCK frequency set to %.3f MHz\n\n", (double)ptr[setClk_index] / MHZ(1)); printInfo(mess); @@ -333,7 +336,7 @@ int CH347Jtag::toggleClk(uint8_t tms, uint8_t tdi, uint32_t len) ptr = obuf; } } - return EXIT_SUCCESS; + return len; } int CH347Jtag::writeTDI(const uint8_t *tx, uint8_t *rx, uint32_t len, bool end) @@ -381,7 +384,7 @@ int CH347Jtag::writeTDI(const uint8_t *tx, uint8_t *rx, uint32_t len, bool end) } unsigned actual_length; if (bits == 0) - return EXIT_SUCCESS; + return len; cmd = (rx) ? CMD_BITS_WR : CMD_BITS_WO; if (get_obuf_length() < (int)(4 + bits * 2)) { flush(); @@ -427,5 +430,5 @@ int CH347Jtag::writeTDI(const uint8_t *tx, uint8_t *rx, uint32_t len, bool end) *rptr &= ~(0x01 << i); } } - return EXIT_SUCCESS; + return len; } diff --git a/src/main.cpp b/src/main.cpp index 4aca9f6..15b0152 100644 --- a/src/main.cpp +++ b/src/main.cpp @@ -13,11 +13,17 @@ #include #include +#ifdef ENABLE_ALTERA_SUPPORT #include "altera.hpp" +#endif +#ifdef ENABLE_ANLOGIC_SUPPORT #include "anlogic.hpp" +#endif #include "board.hpp" #include "cable.hpp" +#ifdef ENABLE_COLOGNECHIP_SUPPORT #include "colognechip.hpp" +#endif #include "common.hpp" #include "cxxopts.hpp" #include "device.hpp" @@ -25,12 +31,24 @@ #include "dfu.hpp" #endif #include "display.hpp" +#ifdef ENABLE_EFINIX_SUPPORT #include "efinix.hpp" +#endif +#ifdef USE_LIBFTDI #include "ftdispi.hpp" +#endif +#ifdef ENABLE_GOWIN_SUPPORT #include "gowin.hpp" -#include "ice40.hpp" +#endif +#ifdef ENABLE_LATTICE_SUPPORT #include "lattice.hpp" +#endif +#ifdef ENABLE_ICE40_SUPPORT +#include "ice40.hpp" +#endif +#ifdef ENABLE_LATTICESSPI_SUPPORT #include "latticeSSPI.hpp" +#endif #ifdef ENABLE_USB_SCAN #include "libusb_ll.hpp" #endif @@ -38,8 +56,12 @@ #include "part.hpp" #include "spiFlash.hpp" #include "rawParser.hpp" +#ifdef ENABLE_XILINX_SUPPORT #include "xilinx.hpp" +#endif +#ifdef ENABLE_SVF_JTAG #include "svf_jtag.hpp" +#endif #ifdef ENABLE_XVC #include "xvc_server.hpp" #endif @@ -298,25 +320,45 @@ int main(int argc, char **argv) if (board && board->manufacturer != "none") { Device *target; if (board->manufacturer == "efinix") { +#ifdef ENABLE_EFINIX_SUPPORT target = new Efinix(spi, args.bit_file, args.file_type, board->reset_pin, board->done_pin, board->oe_pin, args.verify, args.verbose); +#else + printError("Support for Efinix FPGAs was not enabled at compile time"); + return EXIT_FAILURE; +#endif } else if (board->manufacturer == "lattice") { if (board->fpga_part == "ice40") { +#ifdef ENABLE_ICE40_SUPPORT target = new Ice40(spi, args.bit_file, args.file_type, args.prg_type, board->reset_pin, board->done_pin, args.verify, args.verbose); +#else + printError("Support for ICE40 FPGAs was not enabled at compile time"); + return EXIT_FAILURE; +#endif } else if (board->fpga_part == "ecp5") { +#ifdef ENABLE_LATTICESSPI_SUPPORT target = new LatticeSSPI(spi, args.bit_file, args.file_type, args.verbose); +#else + printError("Support for Lattice FPGAs (SSPI mode) was not enabled at compile time"); + return EXIT_FAILURE; +#endif } else { printError("Error (SPI mode): " + board->fpga_part + " is an unsupported/unknown Lattice Model"); return EXIT_FAILURE; } } else if (board->manufacturer == "colognechip") { +#ifdef ENABLE_COLOGNECHIP_SUPPORT target = new CologneChip(spi, args.bit_file, args.file_type, args.prg_type, board->reset_pin, board->done_pin, DBUS6, board->oe_pin, args.verify, args.verbose); +#else + printError("Support for Gowin FPGAs was not enabled at compile time"); + return EXIT_FAILURE; +#endif } else { printError("Error (SPI mode): " + board->manufacturer + " is an unsupported/unknown target"); @@ -468,7 +510,7 @@ int main(int argc, char **argv) return EXIT_SUCCESS; #else - throw std::runtime_error("DFU support: disabled at build time"); + printError("DFU support: disabled at build time"); return EXIT_FAILURE; #endif } @@ -582,6 +624,7 @@ int main(int argc, char **argv) /* detect svf file and program the device */ if (!args.file_type.compare("svf") || args.bit_file.find(".svf") != string::npos) { +#ifdef ENABLE_SVF_JTAG SVF_jtag *svf = new SVF_jtag(jtag, args.verbose); try { svf->parse(args.bit_file); @@ -589,6 +632,11 @@ int main(int argc, char **argv) return EXIT_FAILURE; } return EXIT_SUCCESS; +#else + printError("Support for SVF Jtag was not enabled at compile time"); + delete(jtag); + return EXIT_FAILURE; +#endif } /* check if selected device is supported @@ -606,33 +654,71 @@ int main(int argc, char **argv) Device *fpga; try { if (fab == "xilinx") { +#ifdef ENABLE_XILINX_SUPPORT fpga = new Xilinx(jtag, args.bit_file, args.secondary_bit_file, args.file_type, args.prg_type, args.fpga_part, args.bridge_path, args.target_flash, args.verify, args.verbose, args.skip_load_bridge, args.skip_reset, args.read_dna, args.read_xadc); +#else + printError("Support for Xilinx FPGAs was not enabled at compile time"); + delete(jtag); + return EXIT_FAILURE; +#endif } else if (fab == "altera") { +#ifdef ENABLE_ALTERA_SUPPORT fpga = new Altera(jtag, args.bit_file, args.file_type, args.prg_type, args.fpga_part, args.bridge_path, args.verify, args.verbose, args.flash_sector, args.skip_load_bridge, args.skip_reset); +#else + printError("Support for Altera FPGAs was not enabled at compile time"); + delete(jtag); + return EXIT_FAILURE; +#endif } else if (fab == "anlogic") { +#ifdef ENABLE_ANLOGIC_SUPPORT fpga = new Anlogic(jtag, args.bit_file, args.file_type, args.prg_type, args.verify, args.verbose); -#ifdef USE_LIBFTDI +#else + printError("Support for Anlogic FPGAs was not enabled at compile time"); + delete(jtag); + return EXIT_FAILURE; +#endif } else if (fab == "efinix") { +#ifdef ENABLE_EFINIX_SUPPORT fpga = new Efinix(jtag, args.bit_file, args.file_type, args.prg_type, args.board, args.fpga_part, args.bridge_path, args.verify, args.verbose); +#else + printError("Support for Efinix FPGAs was not enabled at compile time"); + delete(jtag); + return EXIT_FAILURE; #endif } else if (fab == "Gowin") { +#ifdef ENABLE_GOWIN_SUPPORT fpga = new Gowin(jtag, args.bit_file, args.file_type, args.mcufw, args.prg_type, args.external_flash, args.verify, args.verbose, args.user_flash); +#else + printError("Support for Gowin FPGAs was not enabled at compile time"); + delete(jtag); + return EXIT_FAILURE; +#endif } else if (fab == "lattice") { +#ifdef ENABLE_LATTICE_SUPPORT fpga = new Lattice(jtag, args.bit_file, args.file_type, args.prg_type, args.flash_sector, args.verify, args.verbose, args.skip_load_bridge, args.skip_reset); -#ifdef USE_LIBFTDI +#else + printError("Support for Lattice FPGAs was not enabled at compile time"); + delete(jtag); + return EXIT_FAILURE; +#endif } else if (fab == "colognechip") { +#ifdef ENABLE_COLOGNECHIP_SUPPORT fpga = new CologneChip(jtag, args.bit_file, args.file_type, args.prg_type, args.board, args.cable, args.verify, args.verbose); +#else + printError("Support for Gowin FPGAs was not enabled at compile time"); + delete(jtag); + return EXIT_FAILURE; #endif } else { printError("Error: manufacturer " + fab + " not supported"); diff --git a/src/part.hpp b/src/part.hpp index d512a76..7d86411 100644 --- a/src/part.hpp +++ b/src/part.hpp @@ -72,11 +72,13 @@ static std::map fpga_list = { {0x037c4093, {"xilinx", "spartan7", "xc7s25", 6}}, {0x0362f093, {"xilinx", "spartan7", "xc7s50", 6}}, {0x037c8093, {"xilinx", "spartan7", "xc7s75", 6}}, + {0x037c7093, {"xilinx", "spartan7", "xc7s100", 6}}, /* Xilinx Virtex6 */ {0x8424a093, {"xilinx", "virtex6", "xc6vlx130t", 10}}, /* Xilinx 7-Series / Artix7 */ + {0x037c3093, {"xilinx", "artix a7 12t", "xc7a12t", 6}}, {0x0362e093, {"xilinx", "artix a7 15t", "xc7a15", 6}}, {0x037c2093, {"xilinx", "artix a7 25t", "xc7a25", 6}}, {0x0362D093, {"xilinx", "artix a7 35t", "xc7a35", 6}}, @@ -89,15 +91,29 @@ static std::map fpga_list = { {0x03647093, {"xilinx", "kintex7", "xc7k70t", 6}}, {0x0364c093, {"xilinx", "kintex7", "xc7k160t", 6}}, {0x03651093, {"xilinx", "kintex7", "xc7k325t", 6}}, + {0x03747093, {"xilinx", "kintex7", "xc7k355t", 6}}, {0x03656093, {"xilinx", "kintex7", "xc7k410t", 6}}, {0x23752093, {"xilinx", "kintex7", "xc7k420t", 6}}, {0x23751093, {"xilinx", "kintex7", "xc7k480t", 6}}, /* Xilinx 7-Series / Virtex7 */ - {0x03667093, {"xilinx", "virtex7", "xc7vx330t", 6}}, - {0x33691093, {"xilinx", "virtex7", "xc7vx690t", 6}}, + {0x03671093, {"xilinx", "virtex7", "xc7v585t", 6}}, + {0x03667093, {"xilinx", "virtex7", "xc7vx330t", 6}}, + {0x03682093, {"xilinx", "virtex7", "xc7vx415t", 6}}, + {0x03687093, {"xilinx", "virtex7", "xc7vx485t", 6}}, + {0x03692093, {"xilinx", "virtex7", "xc7vx550t", 6}}, + {0x33691093, {"xilinx", "virtex7", "xc7vx690t", 6}}, + {0x03696093, {"xilinx", "virtex7", "xc7vx980t", 6}}, + + {0x036d9093, {"xilinx", "virtex7", "xc7vh580t", 22}}, + + {0x036b3093, {"xilinx", "virtex7", "xc7v2000t", 24}}, + {0x036d5093, {"xilinx", "virtex7", "xc7vx1140t", 24}}, + + {0x036db093, {"xilinx", "virtex7", "xc7vh870t", 38}}, /* Xilinx 7-Series / Zynq */ + {0x13723093, {"xilinx", "zynq", "xc7z007s", 6}}, {0x03722093, {"xilinx", "zynq", "xc7z010", 6}}, {0x03727093, {"xilinx", "zynq", "xc7z020", 6}}, {0x1372c093, {"xilinx", "zynq", "xc7z030", 6}}, @@ -114,19 +130,58 @@ static std::map fpga_list = { {0x03842093, {"xilinx", "virtexus", "xcvu095", 6}}, /* Xilinx Ultrascale+ / Artix */ - {0x04AC2093, {"xilinx", "artixusp", "xcau15p", 6}}, - {0x04A64093, {"xilinx", "artixusp", "xcau25p", 6}}, + {0x04AC4033, {"xilinx", "artixusp", "xcau10p", 6}}, + {0x04AC4093, {"xilinx", "artixusp", "xcau10p", 6}}, + {0x04AC2093, {"xilinx", "artixusp", "xcau15p", 6}}, + {0x04A65093, {"xilinx", "artixusp", "xcau20p", 6}}, + {0x04A64093, {"xilinx", "artixusp", "xcau25p", 6}}, /* Xilinx Ultrascale+ / Kintex */ - {0x04a63093, {"xilinx", "kintexusp", "xcku3p", 6}}, - {0x04a62093, {"xilinx", "kintexusp", "xcku5p", 6}}, + {0x04A63093, {"xilinx", "kintexusp", "xcku3p", 6}}, + {0x04A62093, {"xilinx", "kintexusp", "xcku5p", 6}}, + {0x0484A093, {"xilinx", "kintexusp", "xcku9p", 6}}, + {0x04A4E093, {"xilinx", "kintexusp", "xcku11p", 6}}, + {0x04A51093, {"xilinx", "kintexusp", "xcku11p", 6}}, + {0x04A52093, {"xilinx", "kintexusp", "xcku13p", 6}}, + {0x04A56093, {"xilinx", "kintexusp", "xcku15p", 6}}, + {0x04A59093, {"xilinx", "kintexusp", "xcku15p", 6}}, + {0x04ACF093, {"xilinx", "kintexusp", "xcku19p", 6}}, + {0x04AD3093, {"xilinx", "kintexusp", "xcku19p", 6}}, /* Xilinx Ultrascale+ / Virtex */ - {0x04b31093, {"xilinx", "virtexusp", "xcvu9p", 18}}, - {0x14b79093, {"xilinx", "virtexusp", "xcvu37p", 18}}, + {0x04AEA093, {"xilinx", "virtexusp", "xcvu2p", 6}}, + {0x04B39093, {"xilinx", "virtexusp", "xcvu3p", 6}}, + {0x04B3D093, {"xilinx", "virtexusp", "xcvu3p", 6}}, + + {0x04B2B093, {"xilinx", "virtexusp", "xcvu5p", 12}}, + {0x04B2F093, {"xilinx", "virtexusp", "xcvu5p", 12}}, + {0x04B29093, {"xilinx", "virtexusp", "xcvu7p", 12}}, + {0x04B2D093, {"xilinx", "virtexusp", "xcvu7p", 12}}, + + {0x04B31093, {"xilinx", "virtexusp", "xcvu9p", 18}}, + {0x04B35093, {"xilinx", "virtexusp", "xcvu9p", 18}}, + {0x14B79093, {"xilinx", "virtexusp", "xcvu37p", 18}}, + {0x04B49093, {"xilinx", "virtexusp", "xcvu11p", 18}}, + {0x04B4F093, {"xilinx", "virtexusp", "xcvu11p", 18}}, + + {0x04B51093, {"xilinx", "virtexusp", "xcvu13p", 24}}, + {0x04B55093, {"xilinx", "virtexusp", "xcvu13p", 24}}, + + {0x04BA3093, {"xilinx", "virtexusp", "xcvu15p", 24}}, + {0x04BA1093, {"xilinx", "virtexusp", "xcvu19p", 24}}, + {0x04BA5093, {"xilinx", "virtexusp", "xcvu19p", 24}}, /* Xilinx Ultrascale+ / Spartan */ - {0x04e80093, {"xilinx", "spartanusp", "xcsu35p", 6}}, + {0x04E81093, {"xilinx", "spartanusp", "xcsu10p", 6}}, + {0x04E82093, {"xilinx", "spartanusp", "xcsu25p", 6}}, + {0x04E80093, {"xilinx", "spartanusp", "xcsu35p", 6}}, + {0x04EB1093, {"xilinx", "spartanusp", "xcsu45p", 6}}, + {0x04E90093, {"xilinx", "spartanusp", "xcsu55p", 6}}, + {0x04EB2093, {"xilinx", "spartanusp", "xcsu60p", 6}}, + {0x04E99093, {"xilinx", "spartanusp", "xcsu65p", 6}}, + {0x04E98093, {"xilinx", "spartanusp", "xcsu100p", 6}}, + {0x04EA1093, {"xilinx", "spartanusp", "xcsu150p", 6}}, + {0x04EA0093, {"xilinx", "spartanusp", "xcsu200p", 6}}, /* Xilinx Ultrascale+ / ZynqMP */ /* When powering a zynq ultrascale+ MPSoC, PL Tap and ARM dap diff --git a/src/spiFlashdb.hpp b/src/spiFlashdb.hpp index 49e8207..2e21fc2 100644 --- a/src/spiFlashdb.hpp +++ b/src/spiFlashdb.hpp @@ -585,6 +585,23 @@ static std::map flash_list = { .quad_mask = 0, .global_lock = false, }}, + {0xc22314, { + /* https://datasheet4u.com/pdf-down/M/X/2/MX25V8035F-MACRONIX.pdf */ + .manufacturer = "Macronix", + .model = "MX25V8035F", + .nr_sector = 16, + .sector_erase = true, + .subsector_erase = true, + .has_extended = false, + .tb_otp = true, + .tb_offset = (1 << 3), + .tb_register = CONFR, + .bp_len = 4, + .bp_offset = {(1 << 2), (1 << 3), (1 << 4), (1 << 5)}, + .quad_register = STATR, + .quad_mask = (1 << 6), + .global_lock = false, + }}, {0xef4014, { /* https://cdn-shop.adafruit.com/datasheets/W25Q80BV.pdf */ .manufacturer = "Winbond", diff --git a/src/xilinx.cpp b/src/xilinx.cpp index ebdbe44..2cce842 100644 --- a/src/xilinx.cpp +++ b/src/xilinx.cpp @@ -914,7 +914,7 @@ void Xilinx::program_mem(ConfigBitstreamParser *bitfile) const uint8_t *data = bitfile->getData(); int tx_len; Jtag::tapState_t tx_end; - int burst_len = byte_length / 100; + const int burst_len = (byte_length < 100) ? byte_length : byte_length / 100; ProgressBar progress("Load SRAM", byte_length, 50, _quiet);