diff --git a/spiOverJtag/Makefile b/spiOverJtag/Makefile
index 1734100..1fc1988 100644
--- a/spiOverJtag/Makefile
+++ b/spiOverJtag/Makefile
@@ -14,7 +14,7 @@ XILINX_PARTS := xc3s500evq100 \
 	xc7vx330tffg1157 \
 	xcku040-ffva1156 xcku060-ffva1156 \
 	xcku5p-ffvb676 \
-	xcvu9p-flga2104 xcvu37p-fsvh2892 \
+	xcvu9p-flga2104 xcvu37p-fsvh2892 xcvu7p-flvb2104 \
 	xcau7p-sbvc484 xcau10p-ffvb676 \
 	xcau15p-ffvb676
 XILINX_BIT_FILES := $(addsuffix .bit.gz,$(addprefix spiOverJtag_, $(XILINX_PARTS)))
diff --git a/spiOverJtag/build.py b/spiOverJtag/build.py
index 42f9ccd..43c452c 100755
--- a/spiOverJtag/build.py
+++ b/spiOverJtag/build.py
@@ -163,6 +163,7 @@ if tool in ["ise", "vivado"]:
         "xcku060-ffva1156" : "xcku060_ffva1156",
         "xcvu9p-flga2104"  : "xcvu9p_flga2104",
         "xcvu37p-fsvh2892" : "xcvu37p_fsvh2892",
+        "xcvu7p-flvb2104"  : "xcvu7p_flvb2104",
         "xcku3p-ffva676"   : "xcku3p_ffva676",
         "xcku3p-ffvb676"   : "xcku3p_ffvb676",
         "xcku5p-ffvb676"   : "xcku5p_ffvb676",
@@ -224,6 +225,8 @@ if tool in ["ise", "vivado"]:
                 tool_options = {"part": part + "-2-e"}
             elif part == "xcku3p-ffvb676":
                 tool_options = {"part": part + "-2-e"}
+            elif part == "xcvu7p-flvb2104":
+                tool_options = {"part": part + "-1-e"}
             elif part == "xcvu37p-fsvh2892":
                 tool_options = {"part": part + "-2L-e"}
             elif part in ["xcku040-ffva1156", "xcku060-ffva1156"]:
diff --git a/spiOverJtag/constr_xcvu7p_flvb2104.xdc b/spiOverJtag/constr_xcvu7p_flvb2104.xdc
new file mode 100644
index 0000000..5e42d95
--- /dev/null
+++ b/spiOverJtag/constr_xcvu7p_flvb2104.xdc
@@ -0,0 +1,13 @@
+set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
+set_property CONFIG_VOLTAGE 1.8 [current_design]
+# Table 1-2 from UG570
+set_property CFGBVS GND [current_design]
+
+# Primary QSPI flash
+# Connection done through the STARTUPE3 block
+# sdi_dq0  - PACKAGE_PIN AK12     - QSPI0_DQ0                 Bank   0 - D00_MOSI_0
+# sdo_dq1  - PACKAGE_PIN AJ12     - QSPI0_DQ1                 Bank   0 - D01_DIN_0
+# wpn_dq2  - PACKAGE_PIN AL12     - QSPI0_DQ2                 Bank   0 - D02_0
+# hldn_dq3 - PACKAGE_PIN AL12     - QSPI0_DQ3                 Bank   0 - D03_0
+# csn      - PACKAGE_PIN AG12     - QSPI0_CS_B                Bank   0 - RDWR_FCS_B_0
+# sck      - PACKAGE_PIN AG13     - QSPI_CCLK                 Bank   0 - CCLK_0
diff --git a/spiOverJtag/spiOverJtag_xcvu7p-flvb2104.bit.gz b/spiOverJtag/spiOverJtag_xcvu7p-flvb2104.bit.gz
new file mode 100644
index 0000000..349a83e
Binary files /dev/null and b/spiOverJtag/spiOverJtag_xcvu7p-flvb2104.bit.gz differ
diff --git a/src/part.hpp b/src/part.hpp
index 1a96129..c1d68b5 100644
--- a/src/part.hpp
+++ b/src/part.hpp
@@ -159,6 +159,7 @@ static std::map <uint32_t, fpga_model> fpga_list = {
 	{0x04B2F093, {"xilinx", "virtexusp", "xcvu5p",  12}},
 	{0x04B29093, {"xilinx", "virtexusp", "xcvu7p",  12}},
 	{0x04B2D093, {"xilinx", "virtexusp", "xcvu7p",  12}},
+	{0x14B29093, {"xilinx", "virtexusp", "xcvu7p",  12}},
 
 	{0x04B31093, {"xilinx", "virtexusp", "xcvu9p",  18}},
 	{0x04B35093, {"xilinx", "virtexusp", "xcvu9p",  18}},
diff --git a/src/xilinx.cpp b/src/xilinx.cpp
index 238df43..c68a365 100644
--- a/src/xilinx.cpp
+++ b/src/xilinx.cpp
@@ -174,6 +174,27 @@ static std::map<std::string, std::map<std::string, std::vector<uint8_t>>>
 				{ "BYPASS",      {0b11111111, 0b11111111, 0b11} },
 			}
 		},
+		{
+			/* Xilinx Virtex UltraScale+ */
+			/* <vivado_dir>/data/parts/xilinx/virtexuplus/public/bsdl/xcvu7p_flvb2104.bsd */
+			"virtexusp_vu7p",
+			{
+				{ "USER1",       {0b10100100, 0b0000} },
+				{ "USER2",       {0b11100100, 0b0000} },
+				{ "USER4",       {0b11100100, 0b1000} },
+				{ "CFG_IN",      {0b01100100, 0b0001} }, // CFG_IN_SLR0
+				{ "CFG_OUT",     {0b00100100, 0b0001} }, // CFG_OUT_SLR0
+				{ "USERCODE",    {0b00100100, 0b0010} },
+				{ "IDCODE",      {0b01001001, 0b0010} },
+				{ "ISC_ENABLE",  {0b00010000, 0b0100} },
+				{ "JPROGRAM",    {0b11001011, 0b0010} },
+				{ "JSTART",      {0b00001100, 0b0011} },
+				{ "JSHUTDOWN",   {0b01001101, 0b0011} },
+				{ "ISC_PROGRAM", {0b01010001, 0b0100} },
+				{ "ISC_DISABLE", {0b10010110, 0b0101} },
+				{ "BYPASS",      {0b11111111, 0b1111} }
+			}
+		},
 		{
 			/* Xilinx Virtex UltraScale+ VU19P (xcvu19p_fsva3824) */
 			/* 4-SLR SSI; SLR1 is master per BSDL */
@@ -405,6 +426,8 @@ Xilinx::Xilinx(Jtag *jtag, const std::string &filename,
 		_fpga_family = VIRTEXUSP_FAMILY;
 		if (model == "xcvu19p")
 			_ircode_map = ircode_mapping.at("virtexusp_vu19p");
+		else if (model == "xcvu7p")
+			_ircode_map = ircode_mapping.at("virtexusp_vu7p");
 		else
 			_ircode_map = ircode_mapping.at("virtexusp");
 	} else if (family.substr(0, 8) == "spartan3") {
@@ -879,7 +902,16 @@ float Xilinx::get_spiOverJtag_version()
 	uint8_t jrx[7];
 	uint8_t rx[6];
 
-	_jtag->shiftIR(USER4, _irlen, Jtag::UPDATE_IR);
+	uint32_t idcode = _jtag->get_target_device_id();
+
+	/* Select the correct device and its associated USER4 register */
+	if (fpga_list[idcode].family == "virtexusp" & fpga_list[idcode].model == "xcvu7p") {
+		_jtag->shiftIR(get_ircode(_ircode_map, "USER4"), NULL, _irlen);
+	}
+	else {
+		_jtag->shiftIR(USER4, _irlen, Jtag::UPDATE_IR);
+	}
+
 	printf("jtag_chain_len: %d\n", _jtag_chain_len);
 	if (_jtag_chain_len > 1)
 		_jtag->shiftDR(jtx, NULL, _jtag_chain_len - 1, Jtag::SHIFT_DR);