32 lines
615 B
Plaintext
32 lines
615 B
Plaintext
Test bidi_bridge direction changes and automatic bridging
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Va a 0 pulse 0 3 0 1u 1.2u 500u 1m
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Vb b 0 pulse 0 3 0 1u 1.2u 100u 200u
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Vctl ctl 0 pulse 0 3 10m 1u 1u 10m 20m
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Ainv ctl not_ctl invert
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.model invert d_inverter
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* Transmitter/receiver for an analogue bus line
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.subckt driver in enable out bus
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Atran in enable int tristate
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Arec int out buffer
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Rout int bus 20 // Make bus an analogue node, with bridge
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.ends
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.model buffer d_buffer
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.model tristate d_tristate
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Xa a ctl out_a bus driver
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Xb b not_ctl out_b bus driver
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Rload bus 0 1k
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.control
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save a out_a b out_b
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tran 1m 40m
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plot out_a
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listing e
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.endc
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.end
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