DEVICES --------------------------------------------------------------------------- This file contains the status of devices available in ngspice. This file will be updated every time the device pecific code is altered or changed. This file it is useful in writing ngspice documentation. *************************************************************************** ************************* Linear devices ******************************** *************************************************************************** CAP - Capacitor Initial Release. Ver: N/A Class: C Level: 1 (and only) Status: Enhancements over the original model: - Parallel Multiplier - Temperature difference from circuit temperature - Preliminary technology scaling support - Model capacitance - Cj calculation based on relative dielectric constant and insulator thickness IND - Inductor Initial Release. Ver: N/A Class: L Level: 1 (and only) Status: Enhancements over the original model: - Parallel Multiplier - Temperature difference from circuit temperature - Preliminary technology scaling support - Model inductance - Inductance calculation for toroids or solenoids on the model line. RES - Simple linear resistor Initial Release. Ver: N/A Class: R Level: 1 (and only) Status: Enhancements over the original model: - Parallel Multiplier - Different value for ac analysis - Temperature difference from circuit temperature - Noiseless resistor - Flicker noise - Preliminary technology scaling support *************************************************************************** ********************* Distributed elements ******************************** *************************************************************************** TRA - Transmission line Initial release LTRA - Lossy Transmission line Initial release URC - Uniform distributed RC line Initial release *************************************************************************** **************************** V/I Sources ***************************** *************************************************************************** ASRC - Arbitrary Source Initial Release CCCS - Current Controlled Current Source Initial Release CCVS - Current Controlled Voltage Source Initial Release ISRC - Independent Current Source Initial Release VCCS - Voltage Controlled Current Source Initial Release VCVS - Voltage Controlled Voltage Source Initial Release VSRC - Independent Voltage Source Initial Release *************************************************************************** **************************** Switches **************************** *************************************************************************** CSW - Current controlled switch Initial release SW - Voltage controlled switch Initial release *************************************************************************** **************************** Diodes **************************** *************************************************************************** DIO - Junction Diode Initial Release. Ver: N/A Class: D Level: 1 (and only) Status: Enhancements over the original model: - Parallel Multiplier - Temperature difference from circuit temperature - Forward and reverse knee currents - Periphery (sidewall) effects - Temperature correction of some parameters *************************************************************************** ************************* Bipolar Devices ************************* *************************************************************************** BJT - Bipolar Junction Transistor Initial Release. Ver: N/A Class: Q Level: 1 Status: Enhancements over the original model: - Parallel Multiplier - Temperature difference from circuit temperature BJT2 - Bipolar Junction Trasistor Initial Release. Ver: N/A Class: Q Level: 2 Status: This is the BJT model written by Alan Gillespie to support lateral devices. The model has been hacked by Dietmar Warning fixing some bugs and adding some features (temp. correction on resistors). Enhancements over the original model: - Temperature correction on rc,rb,re - Parallel Multiplier - Temperature difference from circuit temperature *************************************************************************** ***************************** FET Devices *************************** *************************************************************************** JFET - Junction Field Effect transistor Initial Release JFET2 - Jfet PS model Initial release. TO BE TESTED *************************************************************************** *************************** HFET devices *************************** *************************************************************************** HFET - HFET Level 1 Initial release. HFET2 - HFET Level 2 Initial release. *************************************************************************** *************************** MES devices *************************** *************************************************************************** MES - MESfet model Initial release MESA - MESA model Initial release. TO BE TESTED *************************************************************************** **************************** MOS devices **************************** *************************************************************************** MOS1 - Level 1 MOS model Initial Release. Ver: N/A Class: M Level: 1 Status: TO BE TESTED MOS2 - Level 2 MOS model Initial Release. Ver: N/A Class: M Level: 2 Status: TO BE TESTED MOS3 - Level 3 MOS model Initial Release. Ver: N/A Class: M Level: 3 Status: TO BE TESTED MOS6 - Level 6 MOS model Initial Release. Ver: N/A Class: M Level: 6 Status: TO BE TESTED MOS9 - Level 9 MOS model Initial Release. Ver: N/A Class: M Level: 9 Status: TO BE TESTED BSIM1 - BSIM model level 1 Initial Release. Ver: N/A Class: M Level: 4 Status: TO BE TESTED BSIM2 - BSIM model level 2 Initial Release. Ver: N/A Class: M Level: 5 Status: TO BE TESTED BSIM3 - BSIM model level 3 Initial Release. Ver: 3.2.4 Class: M Level: 8 Status: TO BE TESTED This is the BSIM3v3.2.4 model from Berkeley device group. You can find some test netlists with results for this model on its web site. Web site: http://www-device.eecs.berkeley.edu/~bsim3 Enhancements over the original model: - Parallel Multiplier - ACM Area Calculation Method - Multirevision code (supports all 3v3.2 minor revisions) - NodesetFix BSIM3v1 - BSIM model level 3 Initial Release. Ver: N/A Class: M Level: 49 Status: TO BE TESTED AND IMPROVED This is the BSIM3v3.1 model modified by Serban Popescu. This is level 49 model. It is an implementation that supports "HDIF" and "M" parameters. BSIM3v2 - BSIM model level 3 Initial Relese. Ver: 3.2 Class: M Level: 50 Status: TO BE TESTED This is the BSIM3v3.2 model. It is included only for compatibility with existing netlists and parameters files. As always, tests are availabe on the Berkeley's device group site. Web site: http://www-device.eecs.berkeley.edu/~bsim3 BSIM4 - BSIM model level 4 (0.18 um) Initial Release. Ver: 4.2.1 (Updated in rework 14) Class: M Level: 14 Status: TO BE TESTED This is the BSIM4 device model from Berkeley Device Group. Test are available on its web site. Web site: http://www-device.eecs.berkeley.edu/~bsim3/bsim4.html *) Rework 14: Updated to 4.21 YET UNTESTED. HiSIM - Hiroshima-university STARC IGFET Model Initial Release. Ver: 1.2.0 Class: M Level: TBD Status: TO BE TESTED This is the HiSIM model available from Hiroshima University (Ultra-Small Device Engineering Laboratory) Web site: http://home.hiroshima-u.ac.jp/usdl/HiSIM.shtml http://www.starc.or.jp/kaihatu/pdgr/hisim/index.html Enhancements over the original model: - Parallel Multiplier - NodesetFix *************************************************************************** ***************************** SOI Devices **************************** *************************************************************************** BSIM3SOI_FD - SOI model (fully depleted devices) Initial Release. Ver: 2.1. Class: M Level: 11 Status: TO BE TESTED. FD model has been integrated. There is a bsim3soifd directory under the test hierarchy. Test circuits come from the bsim3soi Web site at: http://www-device.eecs.berkeley.edu/~bsimsoi *) rework-14: removed #ifndef NEWCONV code. BSIM3SOI_PD - SOI model (partially depleted devices) Initial Release. Ver: 2.2.1 Class: M Level: 10 Status: TO BE TESTED. PD model has been integrated. There is a bsim3soipd directory under the test hierarchy. Test circuits come from the bsim3soi Web site at: http://www-device.eecs.berkeley.edu/~bsimsoi *) rework-14: removed #ifndef NEWCONV code. BSIM3SOI_DD - SOI Model (dynamic depletion model) Initial Release. Ver: 2.1 Class: M Level: 12 Status: TO BE TESTED. There is a bsim3soidd directory under the test hierarchy. Test circuits come from bsim3soi Web site at: http://www-device.eecs.berkeley.edu/~bsimsoi *) rework-14: removed #ifndef NEWCONV code. SOI3 - STAG SOI3 Model Initial Release. Ver: 2.6 Class: M Level: 62 Status: TO BE TESTED Web site at: http://www.micro.ecs.soton.ac.uk/stag/ *************************************************************************** **************** Other devices not released as source code **************** *************************************************************************** EKV - EKV model Initial Release. Ver: 2.6 Class: M Level: 44 Status: TO BE TESTED Note: This model is not released in source code. You have to obtain the source code from the address below. Web site at: http://legwww.epfl.ch/ekv/