From f6257eba841e0a3a4335d30f650ba82119ac8c44 Mon Sep 17 00:00:00 2001 From: rlar Date: Sun, 14 May 2017 18:31:21 +0200 Subject: [PATCH] Benchmark_test, modify for ngspice --- Benchmark_test/idvd_nmos.sp | 11 ++++++++--- Benchmark_test/idvd_pmos.sp | 13 +++++++++---- Benchmark_test/idvg_nmos.sp | 9 +++++++-- Benchmark_test/idvg_pmos.sp | 9 +++++++-- Benchmark_test/inv_dc.sp | 10 +++++++--- Benchmark_test/inverter_transient.sp | 10 +++++++--- Benchmark_test/modelcard.nmos | 2 +- Benchmark_test/modelcard.pmos | 2 +- Benchmark_test/noise.sp | 7 +++++-- Benchmark_test/ringosc_17.sp | 18 +++++++++++------- 10 files changed, 63 insertions(+), 28 deletions(-) diff --git a/Benchmark_test/idvd_nmos.sp b/Benchmark_test/idvd_nmos.sp index e05e34ad6..bc4685d67 100644 --- a/Benchmark_test/idvd_nmos.sp +++ b/Benchmark_test/idvd_nmos.sp @@ -1,9 +1,9 @@ *Sample netlist for BSIM6.0 *Id-Vd Characteristics for NMOS (T = 27 C) +* (exec-spice "ngspice %s" t) .option abstol=1e-6 reltol=1e-6 post ingold .temp 27 -.hdl "bsim6.va" .include "modelcard.nmos" * --- Voltage Sources --- @@ -11,13 +11,18 @@ vd d 0 dc=1.3 vg g 0 dc=0 vs s 0 dc=0 vb b 0 dc=0 +vt t 0 dc=0 * --- Transistor --- -X1 d g s b nmos W=10e-6 L=10e-6 +M1 d g s b t mn W=10e-6 L=10e-6 * --- DC Analysis --- .dc vd 0.0 1.3 0.01 vg 0.4 1 0.3 .probe dc ids=par'-i(vd)' .probe dc gd=deriv(ids) -.print dc par'ids' par'gd' +.print dc par'ids' par'gd' +.control +run +plot -i(vd) +.endc .end diff --git a/Benchmark_test/idvd_pmos.sp b/Benchmark_test/idvd_pmos.sp index 498eead63..878ddb937 100644 --- a/Benchmark_test/idvd_pmos.sp +++ b/Benchmark_test/idvd_pmos.sp @@ -1,9 +1,9 @@ *Sample netlist for BSIM6.0 *Id-Vd Characteristics for PMOS (T = 27 C) +* (exec-spice "ngspice %s" t) .option abstol=1e-6 reltol=1e-6 post ingold .temp 27 -.hdl "bsim6.va" .include "modelcard.pmos" @@ -12,15 +12,20 @@ vd d 0 dc=-1 vg g 0 dc=0 vs s 0 dc=0 vb b 0 dc=0 +vt t 0 dc=0 * --- Transistor --- -X1 d g s b pmos W=10e-6 L=10e-6 +M1 d g s b t mp W=10e-6 L=10e-6 * --- DC Analysis --- -.dc vd -1.3 0.0 0.01 vg -1 -0.4 -0.3 +.dc vd -1.3 0.0 0.01 vg -1 -0.4 0.3 .probe dc ids=par'i(vd)' .probe dc gd=deriv(ids) -.print dc par'ids' par'gd' +.print dc par'ids' par'gd' +.control +run +plot i(vd) +.endc .end diff --git a/Benchmark_test/idvg_nmos.sp b/Benchmark_test/idvg_nmos.sp index fc91ac081..c33957a50 100644 --- a/Benchmark_test/idvg_nmos.sp +++ b/Benchmark_test/idvg_nmos.sp @@ -1,7 +1,7 @@ *Sample netlist for BSIM6.0 .option abstol=1e-6 reltol=1e-6 post ingold +* (exec-spice "ngspice %s" t) -.hdl "bsim6.va" .include "modelcard.nmos" * --- Voltage Sources --- @@ -9,9 +9,10 @@ vd d 0 dc=50m vg g 0 dc=0.0 vs s 0 dc=0.0 vb b 0 dc=0.0 +vt t 0 dc=0 * --- Transistor --- -X1 d g s b nmos W = 10e-6 L = 10e-6 +M1 d g s b t mn W = 10e-6 L = 10e-6 * --- DC Analysis --- .dc vg -1.3 1.3 0.01 vb -0.3 0 0.1 @@ -20,5 +21,9 @@ X1 d g s b nmos W = 10e-6 L = 10e-6 .probe dc gm=deriv(ids) .probe dc gm2= deriv(gm) .print dc par'ids' par'gm' par'gm2' i(vd) +.control +run +plot -i(vd) +.endc .end diff --git a/Benchmark_test/idvg_pmos.sp b/Benchmark_test/idvg_pmos.sp index 41168a2d2..a15de1f6d 100644 --- a/Benchmark_test/idvg_pmos.sp +++ b/Benchmark_test/idvg_pmos.sp @@ -1,7 +1,7 @@ *Sample netlist for BSIM6.0 +* (exec-spice "ngspice %s" t) .option abstol=1e-6 reltol=1e-6 post ingold -.hdl "bsim6.va" .include "modelcard.pmos" @@ -10,9 +10,10 @@ vd d 0 dc=-0.05 vg g 0 dc=0.0 vs s 0 dc=0.0 vb b 0 dc=0.0 +vt t 0 dc=0 * --- Transistor --- -X1 d g s b pmos W=10e-6 L=10e-6 +M1 d g s b t mp W=10e-6 L=10e-6 * --- DC Analysis --- .dc vg -1.3.0 1.3 0.01 vb 0 -0.3 -0.1 @@ -20,5 +21,9 @@ X1 d g s b pmos W=10e-6 L=10e-6 .probe dc gm=deriv(ids) .probe dc gm2= deriv(gm) .print dc par'ids' par'gm' par'gm2' +.control +run +plot i(vd) +.endc .end diff --git a/Benchmark_test/inv_dc.sp b/Benchmark_test/inv_dc.sp index 6e2f59dd7..14bfbeb28 100644 --- a/Benchmark_test/inv_dc.sp +++ b/Benchmark_test/inv_dc.sp @@ -1,8 +1,8 @@ *Sample netlist for BSIM6.0 *Inverter DC Analysis +* (exec-spice "ngspice %s" t) .option abstol=1e-6 reltol=1e-6 post ingold -.hdl "bsim6.va" .include "modelcard.nmos" .include "modelcard.pmos" * --- Voltage Sources --- @@ -11,8 +11,8 @@ vin vi 0 dc=0.5 * --- Inverter Subcircuit --- .subckt inverter vin vout vdd gnd - Xp1 vout vin vdd gnd pmos W=10u L=10u - Xn1 vout vin gnd gnd nmos W=10u L=10u + mXp1 vout vin vdd gnd 0 mp W=10u L=10u + mXn1 vout vin gnd gnd 0 mn W=10u L=10u .ends * --- Inverter --- @@ -23,4 +23,8 @@ Xinv1 vi vo supply 0 inverter .print dc v(vi) v(vo) +.control +run +plot v(vi) v(vo) +.endc .end diff --git a/Benchmark_test/inverter_transient.sp b/Benchmark_test/inverter_transient.sp index be62e036e..d56c49757 100644 --- a/Benchmark_test/inverter_transient.sp +++ b/Benchmark_test/inverter_transient.sp @@ -1,8 +1,8 @@ *Sample netlist for BSIM6.0 +* (exec-spice "ngspice %s" t) *Inverter Transient .option abstol=1e-6 reltol=1e-6 post ingold -.hdl "bsim6.va" .include "modelcard.nmos" .include "modelcard.pmos" @@ -12,8 +12,8 @@ vin vi 0 dc=0.5 sin (0.5 0.5 1MEG) * --- Inverter Subcircuit --- .subckt inverter vin vout vdd gnd - Xp1 vout vin vdd gnd pmos W=10u L=10u - Xn1 vout vin gnd gnd nmos W=10u L=10u + Mp1 vout vin vdd gnd 0 mp W=10u L=10u + Mn1 vout vin gnd gnd 0 mn W=10u L=10u .ends * --- Inverter --- @@ -27,5 +27,9 @@ Xinv5 4 vo supply 0 inverter .tran 10n 5u .print tran v(vi) v(vo) +.control +run +plot v(vi) v(vo) +.endc .end diff --git a/Benchmark_test/modelcard.nmos b/Benchmark_test/modelcard.nmos index 8e5f5db27..889c20924 100644 --- a/Benchmark_test/modelcard.nmos +++ b/Benchmark_test/modelcard.nmos @@ -1,6 +1,6 @@ *modelcard for BSIM6_BD -.model nmos bsim6 +.model mn NMOS level=16 +LLONG =2E-06 +WWIDE =1E-05 +TYPE =1 diff --git a/Benchmark_test/modelcard.pmos b/Benchmark_test/modelcard.pmos index 44fe2f2dd..3caa068c1 100644 --- a/Benchmark_test/modelcard.pmos +++ b/Benchmark_test/modelcard.pmos @@ -1,6 +1,6 @@ *modelcard for BSIM6_BD -.model pmos bsim6 +.model mp NMOS level=16 +TYPE = -1.0 +toxe = 2.34e-009 +toxp = 1.925e-009 diff --git a/Benchmark_test/noise.sp b/Benchmark_test/noise.sp index ba3aa54a5..80fd67837 100644 --- a/Benchmark_test/noise.sp +++ b/Benchmark_test/noise.sp @@ -1,10 +1,10 @@ *Samle netlist for BSIM6.0 +* (exec-spice "ngspice %s" t) * Drain Noise Simulation .option abstol=1e-6 reltol=1e-6 post ingold .temp 27 -.hdl "bsim6.va" .include "modelcard.nmos" * --- Voltage Sources --- @@ -16,7 +16,7 @@ vbs bulk 0 dc=0v lbias 1 drain 1m cload drain 2 1m rload 2 0 R=1 noise=0 -X1 drain gate 0 bulk nmos W = 10e-6 L = 10e-6 +M1 drain gate 0 bulk0 mn W = 10e-6 L = 10e-6 * --- Analysis --- .op @@ -27,5 +27,8 @@ X1 drain gate 0 bulk nmos W = 10e-6 L = 10e-6 *.print ac v(drain) *.print dc v(drain) .print noise inoise onoise +.control +run +.endc .end diff --git a/Benchmark_test/ringosc_17.sp b/Benchmark_test/ringosc_17.sp index 54ac368c9..08a92c51e 100644 --- a/Benchmark_test/ringosc_17.sp +++ b/Benchmark_test/ringosc_17.sp @@ -1,9 +1,9 @@ *Sample netlist for BSIM6.0 +* (exec-spice "ngspice %s" t) *17-stage ring oscillator .options abstol=1e-6 reltol=1e-6 post ingold dcon=1 -.hdl "bsim6.va" .include "modelcard.nmos" .include "modelcard.pmos" @@ -12,8 +12,8 @@ vdd supply 0 dc=1.0 * --- Inverter Subcircuit --- .subckt inverter vin vout vdd gnd - Xp1 vout vin vdd gnd pmos W=10e-6 L=10e-6 - Xn1 vout vin gnd gnd nmos W=10e-6 L=10e-6 + Mp1 vout vin vdd gnd 0 mp W=10e-6 L=10e-6 + Mn1 vout vin gnd gnd 0 mn W=10e-6 L=10e-6 .ends * --- 17 Stage Ring oscillator --- @@ -42,10 +42,14 @@ Xinv17 17 1 supply 0 inverter .print tran v(1) -.measure tran t1 when v(1)=0.5 cross=1 -.measure tran t2 when v(1)=0.5 cross=7 -.measure tran period param'(t2-t1)/3' -.measure tran delay_per_stage param'period/34' +*.measure tran t1 when v(1)=0.5 cross=1 +*.measure tran t2 when v(1)=0.5 cross=7 +*.measure tran period param'(t2-t1)/3' +*.measure tran delay_per_stage param'period/34' +.control +run +plot v(1) +.endc .end