From f159708362778db821b9d4de2f124a5b3741718f Mon Sep 17 00:00:00 2001
From: rlar <rlar>
Date: Fri, 30 Mar 2018 18:22:36 +0200
Subject: [PATCH] failing testcase, tran freezes

---
 tran-delmin-1.cir | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)
 create mode 100644 tran-delmin-1.cir

diff --git a/tran-delmin-1.cir b/tran-delmin-1.cir
new file mode 100644
index 000000000..fbead58de
--- /dev/null
+++ b/tran-delmin-1.cir
@@ -0,0 +1,27 @@
+* locks when CKTtime += CKTdelta === CKTtime
+
+* (exec-spice "ngspice %s" t)
+*
+* locks at  Reference value :  61039ns
+*
+* CKTdelmin = 4e-21
+*   (log (/ 61039e-9 4e-21) 2) 53.760580844936776
+*
+* probably locks because
+*   CKTtime += CKTdelta  ===  CKTtime
+* thus VSRC won't deliver a changing value
+* thus SW model continues to CKTtrunc
+* thus CKTtime sticks
+
+* PULSE(V1 V2 TD TR TF PW PER)
+v2  1 0  dc=0 pulse (0 1 61029n 20n)
+
+s1  0 0  1 0  smodel
+
+.model smodel sw vt=0.5 ron=100
+
+.control
+tran 0.4n 100u
+.endc
+
+.end