diff --git a/examples/various/adder_mos.cir b/examples/various/adder_mos.cir new file mode 100644 index 000000000..9b85e093e --- /dev/null +++ b/examples/various/adder_mos.cir @@ -0,0 +1,79 @@ + ADDER - 4 BIT ALL-NAND-GATE BINARY ADDER + +*** SUBCIRCUIT DEFINITIONS +.SUBCKT NAND in1 in2 out VDD +* NODES: INPUT(2), OUTPUT, VCC +M1 out in2 Vdd Vdd p1 W=7.5u L=0.35u pd=13.5u ad=22.5p ps=13.5u as=22.5p +M2 net.1 in2 0 0 n1 W=3u L=0.35u pd=9u ad=9p ps=9u as=9p +M3 out in1 Vdd Vdd p1 W=7.5u L=0.35u pd=13.5u ad=22.5p ps=13.5u as=22.5p +M4 out in1 net.1 0 n1 W=3u L=0.35u pd=9u ad=9p ps=9u as=9p +.ENDS NAND + +.SUBCKT ONEBIT 1 2 3 4 5 6 +* NODES: INPUT(2), CARRY-IN, OUTPUT, CARRY-OUT, VCC +X1 1 2 7 6 NAND +X2 1 7 8 6 NAND +X3 2 7 9 6 NAND +X4 8 9 10 6 NAND +X5 3 10 11 6 NAND +X6 3 11 12 6 NAND +X7 10 11 13 6 NAND +X8 12 13 4 6 NAND +X9 11 7 5 6 NAND +.ENDS ONEBIT + +.SUBCKT TWOBIT 1 2 3 4 5 6 7 8 9 +* NODES: INPUT - BIT0(2) / BIT1(2), OUTPUT - BIT0 / BIT1, +* CARRY-IN, CARRY-OUT, VCC +X1 1 2 7 5 10 9 ONEBIT +X2 3 4 10 6 8 9 ONEBIT +.ENDS TWOBIT + +.SUBCKT FOURBIT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 +* NODES: INPUT - BIT0(2) / BIT1(2) / BIT2(2) / BIT3(2), +* OUTPUT - BIT0 / BIT1 / BIT2 / BIT3, CARRY-IN, CARRY-OUT, VCC +X1 1 2 3 4 9 10 13 16 15 TWOBIT +X2 5 6 7 8 11 12 16 14 15 TWOBIT +.ENDS FOURBIT + +*** POWER +VCC 99 0 DC 3.3V + +*** ALL INPUTS +VIN1A 1 0 DC 0 PULSE(0 3 0 5NS 5NS 20NS 50NS) +VIN1B 2 0 DC 0 PULSE(0 3 0 5NS 5NS 30NS 100NS) +VIN2A 3 0 DC 0 PULSE(0 3 0 5NS 5NS 50NS 200NS) +VIN2B 4 0 DC 0 PULSE(0 3 0 5NS 5NS 90NS 400NS) +VIN3A 5 0 DC 0 PULSE(0 3 0 5NS 5NS 170NS 800NS) +VIN3B 6 0 DC 0 PULSE(0 3 0 5NS 5NS 330NS 1600NS) +VIN4A 7 0 DC 0 PULSE(0 3 0 5NS 5NS 650NS 3200NS) +VIN4B 8 0 DC 0 PULSE(0 3 0 5NS 5NS 1290NS 6400NS) + +*** DEFINE NOMINAL CIRCUIT +X1 1 2 3 4 5 6 7 8 9 10 11 12 0 13 99 FOURBIT + +.option noinit acct +.TRAN 500p 6400NS +* save inputs +.save V(1) V(2) V(3) V(4) V(5) V(6) V(7) V(8) + +* use BSIM3 model with default parameters +.model n1 nmos level=49 version=3.3.0 +.model p1 pmos level=49 version=3.3.0 +*.include ./Modelcards/modelcard32.nmos +*.include ./Modelcards/modelcard32.pmos + +.control +pre_set strict_errorhandling +unset ngdebug +*save outputs and specials +save x1.x1.x1.7 V(9) V(10) V(11) V(12) V(13) +run +display +* plot the inputs, use offset to plot on top of each other +plot v(1) v(2)+4 v(3)+8 v(4)+12 v(5)+16 v(6)+20 v(7)+24 v(8)+28 +* plot the outputs, use offset to plot on top of each other +plot v(9) v(10)+4 v(11)+8 v(12)+12 v(13)+16 +.endc + +.END diff --git a/examples/various/agauss_test.cir b/examples/various/agauss_test.cir new file mode 100644 index 000000000..c25327518 --- /dev/null +++ b/examples/various/agauss_test.cir @@ -0,0 +1,48 @@ +* agauss test in ngspice +* generate a sequence of gaussian distributed random numbers. +* test the distribution by sorting the numbers into +* a histogram (buckets) +* chapt. 17.8.6 +.control + define agauss(nom, avar, sig) (nom + avar/sig * sgauss(0)) + let mc_runs = 200 + let run = 0 + let no_buck = 8 $ number of buckets + let bucket = unitvec(no_buck) $ each element contains 1 + let delta = 3e-11 $ width of each bucket, depends + $ on avar and sig + let lolimit = 1e-09 - 3*delta + let hilimit = 1e-09 + 3*delta + + dowhile run < mc_runs + let val = agauss(1e-09, 1e-10, 3) $ get the random number + if (val < lolimit) + let bucket[0] = bucket[0] + 1 $ 'lowest' bucket + end + let part = 1 + dowhile part < (no_buck - 1) + if ((val < (lolimit + part*delta)) & ++ (val > (lolimit + (part-1)*delta))) + let bucket[part] = bucket[part] + 1 + break + end + let part = part + 1 + end + if (val > hilimit) +* 'highest' bucket + let bucket[no_buck - 1] = bucket[no_buck - 1] + 1 + end + let run = run + 1 + end + + let part = 0 + dowhile part < no_buck + let value = bucket[part] - 1 + set value = "$&value" +* print the buckets' contents + echo $value + let part = part + 1 + end + +.endc +.end diff --git a/examples/various/gain_stage.cir b/examples/various/gain_stage.cir new file mode 100644 index 000000000..adc22bfb5 --- /dev/null +++ b/examples/various/gain_stage.cir @@ -0,0 +1,34 @@ +** MOSFET Gain Stage (AC): Benchmarking Implementation of BSIM4.0.0 +** by Weidong Liu 5/16/2000. +** output redirection into file +** chapter 17.8.8 + +M1 3 2 0 0 N1 L=1u W=4u +Rsource 1 2 100k +Rload 3 vdd 25k +Vdd vdd 0 1.8 +Vin 1 0 1.2 ac 0.1 + +.control +ac dec 10 100 1000Meg +plot v(2) v(3) +let flen = length(frequency) $ length of the vector +let loopcounter = 0 +echo output test > text.txt $ start new file test.txt +* loop +while loopcounter lt flen + let vout2 = v(2)[loopcounter] $ generate a single point complex vector + let vout2re = real(vout2) $ generate a single point real vector + let vout2im = imag(vout2) $ generate a single point imaginary vector + let vout3 = v(3)[loopcounter] $ generate a single point complex vector + let vout3re = real(vout3) $ generate a single point real vector + let vout3im = imag(vout3) $ generate a single point imaginary vector + let freq = frequency[loopcounter] $ generate a single point vector + echo bbb "$&freq" "$&vout2re" "$&vout2im" "$&vout3re" "$&vout3im" >> ++text.txt $ append text and data to file (continued fromm line above) + let loopcounter = loopcounter + 1 +end +.endc + +.MODEL N1 NMOS LEVEL=14 VERSION=4.3.0 TNOM=27 +.end diff --git a/examples/various/param_sweep.cir b/examples/various/param_sweep.cir new file mode 100644 index 000000000..79d5869e5 --- /dev/null +++ b/examples/various/param_sweep.cir @@ -0,0 +1,29 @@ +parameter sweep +* resistive divider, R1 swept from start_r to stop_r +* replaces .STEP R1 1k 10k 1k +* chapter 16.13.4.2 + +R1 1 2 1k +R2 2 0 1k + +VDD 1 0 DC 1 +.dc VDD 0 1 .1 + +.control +let start_r = 1k +let stop_r = 10k +let delta_r = 1k +let r_act = start_r +* loop +while r_act le stop_r + alter r1 r_act + run + write dc-sweep.out v(2) + set appendwrite + let r_act = r_act + delta_r +end +plot dc1.v(2) dc2.v(2) dc3.v(2) dc4.v(2) dc5.v(2) ++ dc6.v(2) dc7.v(2) dc8.v(2) dc9.v(2) dc10.v(2) +.endc + +.end