diff --git a/examples/probe/555-timer-2.cir b/examples/probe/555-timer-2.cir
new file mode 100644
index 000000000..bef077378
--- /dev/null
+++ b/examples/probe/555-timer-2.cir
@@ -0,0 +1,97 @@
+ TIMER 555
+ * https://www.electro-tech-online.com/threads/spice-and-555-timer.5806/
+ .SUBCKT UA555  32 30 19 23 33 1  21
+    *           TR O  R  F  TH D  V
+    *
+    * Taken from the Fairchild data book (1982) page 9-3
+    *SYM=UA555
+    *DWG=C:\SPICE\555\UA555.DWG
+    Q4 25 2 3 QP
+    Q5 0 6 3 QP
+    Q6 6 6 8 QP
+    R1 9 21 4.7K
+    R2 3 21 830
+    R3 8 21 4.7K
+    Q7 2 33 5 QN
+    Q8 2 5 17 QN
+    Q9 6 4 17 QN
+    Q10 6 23 4 QN
+    Q11 12 20 10 QP
+    R4 10 21 1K
+    Q12 22 11 12 QP
+    Q13 14 13 12 QP
+    Q14 0 32 11 QP
+    Q15 14 18 13 QP
+    R5 14 0 100K
+    R6 22 0 100K
+    R7 17 0 10K
+    Q16 1 15 0 QN
+    Q17 15 19 31 QP
+    R8 18 23 5K
+    R9 18 0 5K
+    R10 21 23 5K
+    Q18 27 20 21 QP
+    Q19 20 20 21 QP
+    R11 20 31 5K
+    D1 31 24 DA
+    Q20 24 25 0 QN
+    Q21 25 22 0 QN
+    Q22 27 24 0 QN
+    R12 25 27 4.7K
+    R13 21 29 6.8K
+    Q23 21 29 28 QN
+    Q24 29 27 16 QN
+    Q25 30 26 0 QN
+    Q26 21 28 30 QN
+    D2 30 29 DA
+    R14 16 15 100
+    R15 16 26 220
+    R16 16 0 4.7K
+    R17 28 30 3.9K
+    Q3 2 2 9 QP
+    .MODEL DA D (RS=40 IS=1.0E-14 CJO=1PF)
+    .MODEL QP PNP (BF=20 BR=0.02 RC=4 RB=25 IS=1.0E-14 VA=50 NE=2)
+    + CJE=12.4P VJE=1.1 MJE=.5 CJC=4.02P VJC=.3 MJC=.3 TF=229P TR=159N)
+    .MODEL QN NPN (IS=5.07F NF=1 BF=100 VAF=161 IKF=30M ISE=3.9P NE=2
+    + BR=4 NR=1 VAR=16 IKR=45M RE=1.03 RB=4.12 RC=.412 XTB=1.5
+    + CJE=12.4P VJE=1.1 MJE=.5 CJC=4.02P VJC=.3 MJC=.3 TF=229P TR=959P)
+ .ENDS
+
+    **********
+    * Sample Test Circuit for the LM555 Timer: Astable Mode
+    * The LM555 timer model is designed for low frequency
+    * applications, up to 100Hz.
+    .INCLUDE TLC555.LIB
+    .TRAN 10u 100MS
+*    .OPTIONS RELTOL=.0001
+    .SAVE  v(16) v(13) v(17)
+    .SAVE  v(1) v(4) v(3)
+
+    V2 2 0 5
+    VReset res 0 DC 0 PULSE(0 5 1u 1u 1u 30m 50m)
+
+    R3 2 3 1k
+    R4 3 4 5k
+    C3 4 0 0.5u ; 0.15u
+    X2 4  1  res  6  4  3  2 ua555
+*      TR O  R    F  TH D  V
+    RA 2 17 1k ; 5k
+    RB 17 16 5k ; 3k
+    C 16 0 0.5u ; 0.15u
+    RL 2 13 1k
+    XU1 16    15   16   res   13  17   2   0   TLC555
+*      THRES CONT TRIG RESET OUT DISC VCC GND
+
+    .probe all
+
+    .control
+    if $?batchmode
+    else
+      run
+      plot v(16) v(13) v(17) v(1)+6 v(4)+6 v(3)+6
+      display
+      write 555.out all
+    end
+    .endc
+
+    .END
diff --git a/examples/probe/Dual-NMOS-amp.cir b/examples/probe/Dual-NMOS-amp.cir
new file mode 100644
index 000000000..63be12ae1
--- /dev/null
+++ b/examples/probe/Dual-NMOS-amp.cir
@@ -0,0 +1,58 @@
+.title KiCad schematic
+.include "TL072-dual.lib"
+.include "VDMOS_models.lib"
+R15 out GND 1k
+C5 out Net-_C4-Pad1_ 1u
+XU1 Net-_R16-Pad2_ Net-_R4-Pad1_ Net-_C2-Pad1_ GND Net-_C3-Pad1_ Net-_R3-Pad2_ Net-_R17-Pad2_ VCC TL072c
+R6 Net-_M2-Pad3_ Net-_R3-Pad2_ 100k
+R17 Net-_M2-Pad2_ Net-_R17-Pad2_ 100
+M2 Net-_C4-Pad1_ Net-_M2-Pad2_ Net-_M2-Pad3_ Tj2 Tcase2 IRFP240 thermal
+R8 Net-_M2-Pad3_ GND 0.8
+V1 VCC GND 36
+R7 Net-_M1-Pad3_ Net-_C4-Pad1_ 0.1
+C4 Net-_C4-Pad1_ out 10m
+M1 VCC Net-_M1-Pad2_ Net-_M1-Pad3_ Tj1 Tcase1 IRFP240 thermal
+R16 Net-_M1-Pad2_ Net-_R16-Pad2_ 100
+C1 VCC GND 1u
+C2 Net-_C2-Pad1_ in 0.33u
+Vin1 in GND dc 0 ac 1 sin(0 0.5 100 20m)
+Vamb1 Net-_R11-Pad1_ GND {envtemp}
+Rl1 out GND 8
+R13 Net-_C7-Pad1_ Tcase2 0.2
+R14 Net-_R11-Pad1_ Net-_C7-Pad1_ 3
+C7 Net-_C7-Pad1_ GND 300m
+C6 Net-_C6-Pad1_ GND 300m
+R10 Net-_C6-Pad1_ Tcase1 0.2
+R11 Net-_R11-Pad1_ Net-_C6-Pad1_ 3
+R9 GND Tj1 1G
+R12 GND Tj2 1G
+R2 Net-_C3-Pad1_ GND 10k
+C3 Net-_C3-Pad1_ GND 1u
+R4 Net-_R4-Pad1_ GND 1k
+R3 Net-_C2-Pad1_ Net-_R3-Pad2_ 100k
+R1 VCC Net-_C3-Pad1_ 390k
+R5 Net-_C4-Pad1_ Net-_R4-Pad1_ 19.5k
+.ic v(Tj1)={envtemp} v(Tj2)={envtemp}
+.temp {envtemp}
+.param envtemp=25
+.tran 200u 10
+.option RELTOL=.01 ABSTOL=1N VNTOL=10u
+.probe v(tj1) v(tj2) v(tcase1) v(tcase2) v(in) v(out) (all)
+.probe i(m1:s) vd(m2:s, m1:s) vd(M2:1:3)
+.save @m1[id] @m2[id] ; in out
+.control
+set controlswait
+if $?sharedmode
+rusage
+else
+run
+display
+rusage
+settype temperature  tj1 tj2 tcase1 tcase2
+plot tj1 tj2 tcase1 tcase2
+plot in out xlimit 6 6.04
+plot i(u1:vcc-) i(u1:vcc+)*(-1) xlimit 6 6.04
+plot @m1[id] + i(m1:d) xlimit 9 9.04
+end
+.endc
+.end
diff --git a/examples/probe/F5TurboV2-Probe.cir b/examples/probe/F5TurboV2-Probe.cir
new file mode 100644
index 000000000..ad7c671b3
--- /dev/null
+++ b/examples/probe/F5TurboV2-Probe.cir
@@ -0,0 +1,74 @@
+.title Pass Labs F5Turbo V2, schematic and netlist by KiCad
+.include "F5models.lib"
+.probe I(R19) vd(R10) v(in) v(out) vd(Net-_P3-Pad1_, 0)   ; <------------------------------------------
+*.probe (all)   ; <------------------------------------------
+JQ2 Net-_P2-Pad1_ Net-_Q1-Pad2_ Net-_P3-Pad1_ 2SJ74
+R4 0 Net-_P3-Pad1_ 10
+R6 Net-_P2-Pad1_ -32 1k
+MQ5 out Net-_Q5-Pad2_ Net-_D1a1-Pad2_ IRFP240
+R15 Net-_Q5-Pad2_ Net-_P2-Pad1_ 47.5
+R12 Net-_R12-Pad1_ Net-_P2-Pad1_ 2.2k
+RTH2 Net-_D1a1-Pad2_ Net-_R12-Pad1_ 4.7k
+XP2 Net-_P2-Pad1_ -32 -32 RPOT value=5k ratio=0.15
+R21 Net-_D1a1-Pad2_ -32 1
+R10 out Net-_P3-Pad1_ 220
+R9 out Net-_P3-Pad1_ 220
+JQ1 Net-_P1-Pad1_ Net-_Q1-Pad2_ Net-_P3-Pad1_ 2SK170
+R1 Net-_Q1-Pad2_ in 1k
+XP3 Net-_P3-Pad1_ 0 Net-_P3-Pad1_ RPOT value=200 ratio=0.85
+R5 +32 Net-_P1-Pad1_ 1k
+R3 Net-_P3-Pad1_ 0 10
+R2 in 0 47.5k
+.probe i(R2)   ; <------------------------------------------
+R19 +32 Net-_D4a1-Pad1_ 1
+R14 Net-_Q4-Pad2_ Net-_P1-Pad1_ 47.5
+D3a1 +32 Net-_D3a1-Pad1_ DMOD
+D3b1 +32 Net-_D3a1-Pad1_ DMOD
+R20 +32 Net-_D4a1-Pad1_ 1
+D4a1 +32 Net-_D4a1-Pad1_ DMOD
+D4b1 +32 Net-_D4a1-Pad1_ DMOD
+MQ4 out Net-_Q4-Pad2_ Net-_D4a1-Pad1_ IRFP9240
+.probe V(MQ4:3)   ; <------------------------------------------
+R11 Net-_R11-Pad1_ Net-_P1-Pad1_ 2.2k
+RTH1 Net-_D3a1-Pad1_ Net-_R11-Pad1_ 4.7k
+XP1 Net-_P1-Pad1_ +32 +32 RPOT value=5k ratio=0.15
+R13 Net-_Q3-Pad2_ Net-_P1-Pad1_ 47.5
+MQ3 out Net-_Q3-Pad2_ Net-_D3a1-Pad1_ IRFP9240
+.probe i(MQ3, 3) i(MQ5, s)  ; <------------------------------------------
+R18 +32 Net-_D3a1-Pad1_ 1
+R17 +32 Net-_D3a1-Pad1_ 1
+R7 out Net-_P3-Pad1_ 220
+R8 out Net-_P3-Pad1_ 220
+D1b1 Net-_D1a1-Pad2_ -32 DMOD
+R22 Net-_D1a1-Pad2_ -32 1
+R23 Net-_D2a1-Pad2_ -32 1
+R24 Net-_D2a1-Pad2_ -32 1
+D1a1 Net-_D1a1-Pad2_ -32 DMOD
+R16 Net-_Q6-Pad2_ Net-_P2-Pad1_ 47.5
+MQ6 out Net-_Q6-Pad2_ Net-_D2a1-Pad2_ IRFP240
+.probe vd(MQ6: 2:1)   ; <------------------------------------------
+D2a1 Net-_D2a1-Pad2_ -32 DMOD
+D2b1 Net-_D2a1-Pad2_ -32 DMOD
+Rl1 out 0 4
+V1 +32 0 32
+V2 -32 0 -32
+V3 in 0 sin(0 2 1k)
+.probe I(XP2,1)   ; <------------------------------------------
+
+* erroneous .probe parameters 
+.probe (xyz)   ; <------------------------------------------
+.probe Vd(MQ3: 7 : 0)   ; <------------------------------------------
+.probe i(MQ8, s)   ; <------------------------------------------
+
+.tran 10u 10m
+
+
+.control
+run
+display
+rusage
+plot out in
+plot i(mq3:s) i(mq5:s)
+.endc
+
+.end
diff --git a/examples/probe/F5models.lib b/examples/probe/F5models.lib
new file mode 100644
index 000000000..8c396ea03
--- /dev/null
+++ b/examples/probe/F5models.lib
@@ -0,0 +1,63 @@
+* from https://www.diyaudio.com/forums/solid-state/252973-2sk170-2sj74-spice-model-pass-0-4ma.html
+*2SJ74
+*Toshiba Dep-Mode 20mA 400mW LowNoise pkg:TO-92B 2,1,3
+.MODEL 2SJ74 PJF(Beta=92.12m Rs=7.748 Rd=7.748 Lambda=4.464m
++Vto=-.5428 Cgd=85.67p Pb=.3905 Fc=.5
++Cgs=78.27p Is=12.98p
++Kf=26.64E-18 Af=1)
+
+*2SK170
+* 20mA 400mW LowNoise Dep-Mode pkg:TO-92B 3,1,2
+.MODEL 2SK170 NJF(Beta=59.86m Rs=4.151 Rd=4.151 Lambda=1.923m
++Vto=-.5024 Cgd=20p Pb=.4746 Fc=.5
++Cgs=25.48p Is=8.477p
++Kf=111.3E-18 Af=1)
+
+.subckt RPOT 1 2 3
+R1 1 2 {value*ratio + 1m}
+R2 2 3 {value*(1-ratio)+ 1m}
+* below are default parameters, which are required by some simulators
+.param value=1k
+.param ratio=1
+.ends
+
+.model IRFP240 VDMOS nchan
++ Vto=4 Kp=5.9 Lambda=.001 Theta=0.015 ksubthres=.27
++ Rd=61m Rs=18m Rg=3 Rds=1e7
++ Cgdmax=2.45n Cgdmin=10p a=0.3 Cgs=1.2n
++ Is=60p N=1.1 Rb=14m XTI=3
++ Cjo=1.5n Vj=0.8 m=0.5
++ tcvth=0.0065 MU=-1.27 texp0=1.5
++ Rthjc=0.4 Cthj=0.1
++ mtriode=0.8
+
+.model IRFP9240 VDMOS pchan
++ Vto=-4 Kp=8.8 Lambda=.003 Theta=0.08 ksubthres=.35
++ Rd=180m Rs=50m Rg=3 Rds=1e7
++ Cgdmax=1.25n Cgdmin=50p a=0.23 Cgs=1.15n
++ Is=150p N=1.3 Rb=16m XTI=2
++ Cjo=1.3n Vj=0.8 m=0.5
++ tcvth=0.004 MU=-1.27 texp0=1.5
++ Rthjc=0.4 Cthj=0.1
++ mtriode=0.6
+
+.model DMOD D
+
+* Thermistor model
+.subckt th n1 nt n2 
+.param B=3977
+.param R25=4700
+*control node
+Ctherm1 n1 0 100p
+Ctherm2 n2 0 100p
+Rtherm n1 n2 R = {R25*exp(B*(1/(v(nt)+273.15)-1/(25+273.15)))}
+.ends
+
+* generic relay model
+.subckt genrelay out1 out2 in1 in2
+.param ron = 10m
+S1 out1 out2 in1 in2 SW
+.MODEL SW VSWITCH(VON=4V VOFF=1V RON={ron} ROFF=100K)
+.ends
+
+
diff --git a/examples/probe/TL072-dual.lib b/examples/probe/TL072-dual.lib
new file mode 100644
index 000000000..7fea49b28
--- /dev/null
+++ b/examples/probe/TL072-dual.lib
@@ -0,0 +1,6 @@
+* A dual opamp ngspice model
+.subckt TL072c 1out 1in- 1in+ vcc- 2in+ 2in- 2out vcc+
+.include TL072.301
+XU1A 1in+ 1in- vcc+ vcc- 1out TL072
+XU1B 2in+ 2in- vcc+ vcc- 2out TL072
+.ends
diff --git a/examples/probe/TL072.301 b/examples/probe/TL072.301
new file mode 100644
index 000000000..ad09a6cb9
--- /dev/null
+++ b/examples/probe/TL072.301
@@ -0,0 +1,43 @@
+* TL072 OPERATIONAL AMPLIFIER "MACROMODEL" SUBCIRCUIT
+* CREATED USING PARTS RELEASE 4.01 ON 06/16/89 AT 13:08
+* (REV N/A)      SUPPLY VOLTAGE: +/-15V
+* CONNECTIONS:   NON-INVERTING INPUT
+*                | INVERTING INPUT
+*                | | POSITIVE POWER SUPPLY
+*                | | | NEGATIVE POWER SUPPLY
+*                | | | | OUTPUT
+*                | | | | |
+.SUBCKT TL072    1 2 3 4 5
+*
+  C1   11 12 3.498E-12
+  C2    6  7 15.00E-12
+  DC    5 53 DX
+  DE   54  5 DX
+  DLP  90 91 DX
+  DLN  92 90 DX
+  DP    4  3 DX
+  EGND 99  0 POLY(2) (3,0) (4,0) 0 .5 .5
+  FB    7 99 POLY(5) VB VC VE VLP VLN 0 4.715E6 -5E6 5E6 5E6 -5E6
+  GA    6  0 11 12 282.8E-6
+  GCM   0  6 10 99 8.942E-9
+  ISS   3 10 DC 195.0E-6
+  HLIM 90  0 VLIM 1K
+  J1   11  2 10 JX
+  J2   12  1 10 JX
+  R2    6  9 100.0E3
+  RD1   4 11 3.536E3
+  RD2   4 12 3.536E3
+  RO1   8  5 150
+  RO2   7 99 150
+  RP    3  4 2.143E3
+  RSS  10 99 1.026E6
+  VB    9  0 DC 0
+  VC    3 53 DC 2.200
+  VE   54  4 DC 2.200
+  VLIM  7  8 DC 0
+  VLP  91  0 DC 25
+  VLN   0 92 DC 25
+.MODEL DX D(IS=800.0E-18)
+.MODEL JX PJF(IS=15.00E-12 BETA=270.1E-6 VTO=-1)
+.ENDS
+
\ No newline at end of file
diff --git a/examples/probe/TLC555.LIB b/examples/probe/TLC555.LIB
new file mode 100644
index 000000000..cebcf9aee
--- /dev/null
+++ b/examples/probe/TLC555.LIB
@@ -0,0 +1,438 @@
+* TLC555
+*****************************************************************************
+* (C) Copyright 2011 Texas Instruments Incorporated. All rights reserved.                                            
+*****************************************************************************
+** This model is designed as an aid for customers of Texas Instruments.
+** TI and its licensors and suppliers make no warranties, either expressed
+** or implied, with respect to this model, including the warranties of 
+** merchantability or fitness for a particular purpose.  The model is
+** provided solely on an "as is" basis.  The entire risk as to its quality
+** and performance is with the customer.
+*****************************************************************************
+*
+* This model is subject to change without notice. Texas Instruments
+* Incorporated is not responsible for updating this model.
+*
+*****************************************************************************
+*
+** Released by: Analog eLab Design Center, Texas Instruments Inc.
+* Part: TLC555
+* Date: 13JUN2011
+* Model Type: ALL IN ONE
+* Simulator: PSPICE
+* Simulator Version: 16.0.0.p001
+* EVM Order Number: N/A 
+* EVM Users Guide: N/A
+* Datasheet: SLFS043F - SEPTEMBER 1983 - REVISED FEBRUARY 2005
+*
+* Model Version: 1.0
+*
+*****************************************************************************
+*
+* Updates:
+*
+* Version 1.0 : 
+* Release to Web
+*
+*****************************************************************************
+*
+* THIS MODEL IS APPLICABLE FOR TLC555 & TLC556
+*
+*****************************************************************************
+.SUBCKT TLC555 THRES CONT TRIG RESET OUT DISC VCC GND
+XD8          GND RESI   D_Z18V
+XD7          GND RESET   D_Z18V
+XR2          RESET RESI   TLC55X_RWELL
++ PARAMS: W=50u L=20u 
+XD2          GND TRGI   D_Z18V
+XD1          GND TRIG   D_Z18V
+XR3          TRIG TRGI   TLC55X_RWELL
++ PARAMS: W=50u L=20u 
+XD4          GND THRI   D_Z18V
+XD3          GND THRES   D_Z18V
+XR2_2        THRES THRI   TLC55X_RWELL
++ PARAMS: W=50u L=20u 
+XD6          GND CONTI   D_Z18V
+XD5          GND CONT   D_Z18V
+XR2_3        CONT CONTI   TLC55X_RWELL
++ PARAMS: W=50u L=20u 
+XMN15        GOUT GND QFF GND   MDSWN
++ PARAMS: W=100U L=10U M=7
+XMP15        GOUT VCC QFF GND   MDSWP
++ PARAMS: W=195U L=10U M=9
+XMN3         GND TRGO 23   IIMIRRN
++ PARAMS: W1=170U L1=18U M1=1 W2=170U L2=18U M2=1 IDIN=1U 
+XMN5         GND THRS 25   IIMIRRN
++ PARAMS: W1=13U L1=26U M1=1 W2=52U L2=13U M2=2 IDIN=50N 
+XMp9         VCC RESO 15 GND   IMIRRP
++ PARAMS: W=112U L=15U M=2 IO=2U 
+XMp6         VCC 25 15 GND   IMIRRP
++ PARAMS: W=18U L=26U M=1 IO=100n 
+XMp5         VCC TRGS 15 GND   IMIRRP
++ PARAMS: W=112U L=15U M=2 IO=2U 
+XMp1         VCC THRO 29   IIMIRRP
++ PARAMS: W1=172U L1=15U M1=1 W2=172U L2=15U M2=1 IDIN=1U 
+XIB          VCC GND 15   IBIAS
+XRSFF        TRGO THRO RESO QFF 30 VCC GND   RR1SFF
++ PARAMS: VOUTH=1 VOUTL=0 RIN=1E12 DELAY=30N ROUT=10
+XMN9         TRGO RESO GND   MSWN
++ PARAMS: W=100U L=10U M=1 
+XMN17        DISC GOUT GND GND   TLC55X_NMOS_HV
++ PARAMS: W=350U L=10U M=20 
+XMN16        OUT GOUT GND GND   TLC55X_NMOS_HV
++ PARAMS: W=175U L=10U M=20 
+XMP16        OUT GOUT VCC VCC   TLC55X_PMOS_HV
++ PARAMS: W=270u L=10u M=7 
+XMN10        RESO RESI GND GND   TLC55X_NMOS_HV_L1
++ PARAMS: W=100u L=10u M=1 
+XMN2         THRO THRI THRS GND   TLC55X_NMOS_MV
++ PARAMS: W=170u L=18u M=2 
+XMP4         TRGO TRGI TRGS VCC   TLC55X_PMOS_MV
++ PARAMS: W=172u L=15u M=2 
+XMP3         23 TRGC TRGS VCC   TLC55X_PMOS_MV
++ PARAMS: W=172u L=15u M=2 
+XMPR1F       GND GND 32 TRGC   TLC55X_PMOS_LV
++ PARAMS: W=20U L=15U M=1
+XMPR1E       32 32 TRGC TRGC   TLC55X_PMOS_LV
++ PARAMS: W=20U L=15U M=1
+XMPR1D       TRGC TRGC 33 CONTI   TLC55X_PMOS_LV
++ PARAMS: W=20U L=15U M=1
+XMPR1C       33 33 CONTI CONTI   TLC55X_PMOS_LV
++ PARAMS: W=20U L=15U M=1
+XMPR1B       CONTI CONTI 34 VCC   TLC55X_PMOS_LV
++ PARAMS: W=20u L=15u M=1 
+XMPR1A       34 34 VCC VCC   TLC55X_PMOS_LV
++ PARAMS: W=20u L=15u M=1 
+XMN1         29 CONTI THRS GND   TLC55X_NMOS_MV
++ PARAMS: W=170u L=18u M=2 
+.ENDS TLC555
+
+.SUBCKT TLC55X_NMOS_HV  D G S B PARAMS: W = 100U L = 10U M = 1
+M1 D G S B TLC55X_NMOSD_HV W = {W} L = {L} M = {M} AD={W*LS} AS={W*LS} PD={W + 2*LS} PS={W + 2*LS} 
++ NRD={LS/W} NRS={LS/W}
+.ENDS
+*$
+.SUBCKT TLC55X_NMOS_HV_L1  D G S B PARAMS: W = 100U L = 10U M = 1
+M1 D G S B TLC55X_NMOSD_HV_L1 W = {W} L = {L} M = {M} AD={W*LS} AS={W*LS} PD={W + 2*LS} PS={W + 2*LS} 
++ NRD={LS/W} NRS={LS/W}
+.ENDS
+*$
+.SUBCKT TLC55X_NMOS_MV  D G S B PARAMS: W = 100U L = 10U M = 1
+M1 D G S B TLC55X_NMOSD_MV W = {W} L = {L} M = {M} AD={W*LS} AS={W*LS} PD={W + 2*LS} PS={W + 2*LS} 
++ NRD={LS/W} NRS={LS/W}
+.ENDS
+*$
+.SUBCKT TLC55X_NMOS_LV  D G S B PARAMS: W = 100U L = 10U M = 1
+M1 D G S B TLC55X_NMOSD_LV W = {W} L = {L} M = {M} AD={W*LS} AS={W*LS} PD={W + 2*LS} PS={W + 2*LS} 
++ NRD={LS/W} NRS={LS/W}
+.ENDS
+*$
+.MODEL TLC55X_NMOSD_HV NMOS LEVEL=3 L=10U W=100U KP={KPN} VTO={VTOHN} LAMBDA=2E-3 THETA=1.8E-01
++ CJ={CJN} CJSW={CJSWN} CGSO={CGSON} CGDO={CGDON} RSH= 10 PB=0.65 LD= 70N TOX={TOX}
+*$
+.MODEL TLC55X_NMOSD_HV_L1 NMOS LEVEL=1 L=10U W=100U KP={KPN} VTO={VTOHN} LAMBDA=2E-3 
++ CJ={CJN} CJSW={CJSWN} CGSO={CGSON} CGDO={CGDON} RSH= 10 PB=0.65 LD= 70N TOX={TOX}
+*$
+.MODEL TLC55X_NMOSD_MV NMOS LEVEL=1 L=10U W=100U KP={KPN} VTO={VTOMN} LAMBDA=2E-3 
++ CJ={CJNCG} CJSW={CJSWNCG} CGSO={CGSONCG} CGDO={CGDONCG} PB=0.65 LD= 70N TOX={TOXCG}
+*+ RSH= 10
+*$
+.MODEL TLC55X_NMOSD_LV NMOS LEVEL=1 L=10U W=100U KP={KPN} VTO={VTON} LAMBDA=2E-3 
++ CJ={CJN} CJSW={CJSWN} CGSO={CGSON} CGDO={CGDON} PB=0.65 LD= 300N TOX={TOX}
+*+ RSH= 10
+*$
+.SUBCKT TLC55X_PMOS_HV  D G S B PARAMS: W = 100U L = 10U M = 1
+M1 D G S B TLC55X_PMOSD_HV W = {W} L = {L} M = {M} AD={W*LS} AS={W*LS} PD={W + 2*LS} PS={W + 2*LS} 
++ NRD={LS/W} NRS={LS/W}
+.ENDS
+*$
+.SUBCKT TLC55X_PMOS_MV  D G S B PARAMS: W = 100U L = 10U M = 1
+M1 D G S B TLC55X_PMOSD_MV W = {W} L = {L} M = {M} AD={W*LS} AS={W*LS} PD={W + 2*LS} PS={W + 2*LS} 
++ NRD={LS/W} NRS={LS/W}
+.ENDS
+*$
+.SUBCKT TLC55X_PMOS_LV  D G S B PARAMS: W = 100U L = 10U M = 1
+M1 D G S B TLC55X_PMOSD_LV W = {W} L = {L} M = {M} AD={W*LS} AS={W*LS} PD={W + 2*LS} PS={W + 2*LS} 
++ NRD={LS/W} NRS={LS/W}
+.ENDS
+*$
+.MODEL TLC55X_PMOSD_HV PMOS LEVEL=3 L=10U W=100U KP={KPP} VTO={-VTOHP} LAMBDA=2E-3 THETA=2.2E-01
++ CJ={CJP} CJSW={CJSWP} CGSO={CGSOP} CGDO={CGDOP} RSH=10 PB=0.65 LD=70N TOX={TOX}
+*$
+.MODEL TLC55X_PMOSD_MV PMOS LEVEL=1 L=10U W=100U KP={KPP} VTO={-VTOMP} LAMBDA=2E-3 
+*+ CJ={CJP} CJSW={CJSWP} CGSO={CGSOP} CGDO={CGDOP} PB=0.65 LD=70N TOX={TOX}
++ CJ={CJNCG} CJSW={CJSWNCG} CGSO={CGSONCG} CGDO={CGDONCG} PB=0.65 LD= 70N TOX={TOXCG}
+*+ RSH= 10
+*$
+.MODEL TLC55X_PMOSD_LV PMOS LEVEL=1 L=10U W=100U KP={KPP} VTO={-VTOP} LAMBDA=2E-3 
++ CJ={CJP} CJSW={CJSWP} CGSO={CGSOP} CGDO={CGDOP}  PB=0.65 LD=300N TOX={TOX}
+*+ RSH= 10
+*$
+.SUBCKT TLC55X_RWELL  1 2 PARAMS: W = 10U L = 100U
+XR1 1 2 TLC55X_RWELLD PARAMS: W = {W} L = {L} 
+.ENDS
+*$
+.SUBCKT TLC55X_RWELLD  1 2 PARAMS: W = 10U L = 100U
+R1 1 2 {RSW*L/W}
+.ENDS
+*$
+.SUBCKT TLC55X_RNSD  1 2 PARAMS: W = 10U L = 100U
+XR1 1 2 TLC55X_RNSD_D PARAMS: W = {W} L = {L} 
+.ENDS
+*$
+.SUBCKT TLC55X_RNSD_D  1 2 PARAMS: W = 10U L = 100U
+R1 1 2 {RSN*L/W}
+.ENDS
+*$
+.SUBCKT TLC55X_RC  1 2 PARAMS: WW = 10U LW = 100U WNSD = 10U LNSD = 100U
+XR1 1 2 TLC55X_RC_D PARAMS: WW = {WW} LW = {LW}  WNSD = {WNSD}  LNSD = {LNSD} 
+.ENDS
+*$
+.SUBCKT TLC55X_RC_D  1 2 PARAMS:  WW = 10U LW = 100U WNSD = 10U LNSD = 100U
+R1 1 2 {RSW*LW/WW + RSN*LNSD/WNSD}
+.ENDS
+*
+.SUBCKT IBIAS VCC GND VIB
+*
+.PARAM M1 = 8
+.PARAM M2 = 5
+.PARAM MP = 1
+.PARAM WP = 13U
+.PARAM WN = 130U
+.PARAM LPE = {36U - LDP}
+.PARAM LNE = {13U - LDN}
+.PARAM BP = {MP*(WP/LPE)*(KPP/2)}
+.PARAM WW = 13U
+.PARAM LW = 213U
+.PARAM WNN = 25U
+.PARAM LNN = 87U
+.PARAM R1 = {(RSW*LW/WW + RSN*LNN/WNN)}
+.PARAM K2 = {M2*(WN/LNE)*(KPN/2)}
+.PARAM MR = {M2/M1}
+*
+R1 VIB GND {VBMUL}
+GB  VCC VIB  VALUE = {LIMIT( IF ( V(VCC,GND) > VTOHP, BP*PWR(V(VCC,GND)-VTOHP, 2), 0), 
++ (1 + 1*LAMBDA*(V(VCC,GND) - VTOHN))*PWR(( 1 - SQRT(MR/(1+2*LAMBDA*(V(VCC,GND) - VTOHP))) )/R1, 2)/K2, 0)}
+R2 VIB VCC {RPAR}
+.ENDS
+
+.SUBCKT IMIRRP VCC IO VIB GND PARAMS: W = 100U L = 10U M = 1 IO = 1U
+*
+.PARAM MP = 1
+.PARAM WP = 13U
+.PARAM LPE = {36U - LDP}
+.PARAM LE = {L - LDP}
+.PARAM MR = { M*W/LE/(MP*WP/LPE)/VBMUL }
+.PARAM B1 = { (KPP/2*MP*WP/LPE)*VBMUL }
+.PARAM IS = 1E-12
+.PARAM N = {VTOHP/(VT*Log(1 + IO/IS))}
+*
+GB VCC IO VIB GND {MR}
+R1 VCC IO {RPAR}
+C1 VCC IO {M*(CBDJ*CJP*LS*W + CBDS*CJSWP*(2*LS + W))}
+V1 VCC 10 {VTOHP}
+D1 IO  10  DMOD1
+.MODEL DMOD1 D (IS={IS} N={N} )
+.ENDS
+
+.SUBCKT IIMIRRP VCC IO II PARAMS: W1 = 100U L1 = 10U M1 = 1 W2 = 100U L2= 10U M2 = 2 IDIN = 1U
+*
+.PARAM L1E = {L1 - LDP}
+.PARAM L2E = {L2 - LDP}
+.PARAM B1 = {M1*(W1/L1)*(KPP/2)}
+.PARAM MR = {M2*W2/L2E/(M1*W1/L1E)}
+.PARAM RDS = {1/(2*SQRT(M2*(W2/L2E)*(KPP/2)*IDIN))}
+.PARAM IS = 1E-12
+.PARAM NP = {VTOP/(VT*Log(1 + IDIN/IS))}
+*
+FB VCC IO V1 {MR}
+R1 VCC IO {RPAR}
+C1 VCC IO {M2*(CBDJ*CJP*LS*W2 + CBDS*CJSWP*(2*LS + W2))}
+D1 IO  10  DMODP
+V1 VCC 10 {VTOP}
+R2 II 10  {RDS}
+C2 VCC II {M1*(CBDJ*CJP*LS*W1 + CBDS*CJSWP*(2*LS + W1)) + 2/3*COX*(M1*W1*L1E + M2*W2*L2E) + M1*CGSOP*W1}
+C3 II IO {CGDOP*W2}
+.MODEL DMODP D (IS={IS} N={NP} )
+.ENDS
+
+.SUBCKT IIMIRRN GND IO II PARAMS: W1 = 100U L1 = 10U M1 = 1 W2 = 100U L2= 10U M2 = 2 IDIN = 1U
+*
+.PARAM L1E = {L1 - LDN}
+.PARAM L2E = {L2 - LDN}
+.PARAM B1 = {M1*(W1/L1)*(KPN/2)}
+.PARAM MR = { M2*W2/L2E/(M1*W1/L1E) }
+.PARAM RDS = {1/(2*SQRT(M2*(W2/L2E)*(KPN/2)*IDIN))}
+.PARAM IS = 1E-12
+.PARAM NN = {VTON/(VT*Log(1 + IDIN/IS))}
+*
+FB IO GND V1 {MR}
+R1 IO GND {RPAR}
+C1 IO GND {M2*(CBDJ*CJN*LS*W2 + CBDS*CJSWN*(2*LS + W2))}
+D1 10 IO  DMODN
+V1 10 GND {VTON}
+R2 II 10  {RDS}
+C2 II GND {M1*(CBDJ*CJN*LS*W1 + CBDS*CJSWN*(2*LS + W1)) + 2/3*COX*(M1*W1*L1E + M2*W2*L2E) + M1*CGSON*W1}
+C3 II IO {M2*CGDON*W2}
+.MODEL DMODN D (IS={IS} N={NN} ) 
+.ENDS
+
+.SUBCKT MDSWP D S DG GND PARAMS: W = 100U L = 10U M = 1
+*
+.PARAM LE = {L - LDP}
+*
+S1 D S DG GND SWN
+C1 D S {M*(CBDJ*CJP*LS*W + CBDS*CJSWP*(2*LS + W))} 
+*D B
+.MODEL SWN VSWITCH ( VON = {0.49} VOFF = {0.55} RON={1/(2*M*(W/LE)*(KPP/2)*10)} ROFF={1G} )
+.ENDS
+
+.SUBCKT MDSWN D S DG GND PARAMS: W = 100U L = 10U M = 1
+*
+.PARAM LE = {L - LDN}
+*
+S1 D S DG GND SWN
+C1 D S {M*(CBDJ*CJN*LS*W + CBDS*CJSWN*(2*LS + W))} 
+*D B
+.MODEL SWN VSWITCH ( VON = {0.55} VOFF = {0.49} RON={1/(2*M*(W/LE)*(KPN/2)*10)} ROFF={1G} )
+.ENDS
+
+.SUBCKT MSWN D G S PARAMS: W = 100U L = 10U M = 1
+*
+.PARAM LE = {L - LDN}
+*
+*C1 D S {M*(CBDJ*CJN*LS*W + CBDS*CJSWN*(2*LS + W))} 
+*D B
+*C2 G S {M*2/3*COX*(W*LE) + CGSON*W}
+*C3 G D {CGDON*W}
+S1 D S G S SWN
+.MODEL SWN VSWITCH ( VON = {VTON+1} VOFF = {VTON} RON={1/(2*M*(W/L)*(KPN/2)*10)} ROFF={1G} )
+.ENDS
+*
+* CONNECTIONS:   A
+*                |    C
+*                |    |
+.SUBCKT D_Z18V   1    2
+D1 1 2  DZ_18V
+.ENDS 
+
+.PARAM ISZ = 5P
+.PARAM NZ = {0.3/(VT*Log(1 + 5.0M/ISZ))}
+.MODEL DZ_18V D( IS={ISz} N={Nz} BV=18.0 IBV=5.0M EG={8*Nz*VT})
+
+.SUBCKT RR1SFF S R R1 Q  Q_ VCC GND
++ PARAMS: VOUTH=5.0 VOUTL=0 RIN=1E12 DELAY=10N ROUT=10
+.PARAM W1 = 100U 
+.PARAM L1 = 10U 
+.PARAM W2 = 100U 
+.PARAM L2= 10U 
+.PARAM W3 = 10U 
+.PARAM L3 = 25U 
+.PARAM W4 = 10U 
+.PARAM L4= 100U 
+*
+XU1     Q GND S GND Q_ GND   COMP2INPNORSD
++ PARAMS: ROUT={ROUT} DELAYLH={1N} DELAYHL={1N} VOUTH={VOUTH} VOUTL={VOUTL} 
++ VTHRES1={0.5*(VOUTH-VOUTL)} VTHRES2={VTOCN}
+XU2     VCC R R1 GND Q_ GND Q VCC GND   COMP3INPNORSD
++ PARAMS: ROUT={ROUT} DELAYLH={15N} DELAYHL={1N} VOUTH={VOUTH} VOUTL={VOUTL} 
++ VTHRES1={VTOCP} VTHRES2={VTOCN} VTHRES3={0.49*(VOUTH-VOUTL)}
+*C1 S GND {0.5*COX*(W1*L1) + CGSON*W1}
+*C2 R VCC {0.5*COX*(W2*L2) + CGSOP*W2}
+*C3 R1 GND {0.5*COX*(W3*L3) + CGSON*W3}
+*C4 R1 VCC {0.5*COX*(W4*L4) + CGSOP*W4}
+.ENDS
+
+.SUBCKT COMP2INPNORSD IN1+ IN1- IN2+ IN2- OUT GND
++ PARAMS: ROUT=0 DELAYLH=0 DELAYHL=0 VOUTH=0 VOUTL=0 VTHRES1=0 VTHRES2=0
+*
+.PARAM TDELLH = {IF ( (DELAYLH < 1E-9) , 1E-9, DELAYLH ) } 
+.PARAM TDELHL = {IF ( (DELAYHL < 1E-9) , 1E-9, DELAYHL ) } 
+.PARAM RO = {IF ( (TDEL > 1E-15) & (ROUT < 1), 1, ROUT ) } 
+.PARAM TDEL = {(TDELLH+TDELHL)/2}
+.PARAM COUT={TDEL/(0.693*(RO+1U))}
+.PARAM RDELLH = {TDELLH/(0.693*(COUT+1F))}
+.PARAM RDELHL = {TDELHL/(0.693*(COUT+1F))}
+
+EOUT OUT GND VALUE= { IF ( (V(IN1+,IN1-) > {VTHRES1}) | (V(IN2+,IN2-) > {VTHRES2}), 
++ VOUTL + RDELLH*I(EOUT), VOUTH + RDELHL*I(EOUT) ) }
+COUT OUT GND {COUT}
+.ENDS COMP2INPNORSD
+
+.SUBCKT COMP3INPNORSD IN1+ IN1- IN2+ IN2- IN3+ IN3- OUT VCC GND
++ PARAMS: ROUT=0 DELAYLH=0 DELAYHL=0 VOUTH=0 VOUTL=0 VTHRES1=0 VHYST1=0 VTHRES2=0 VHYST2=0 VTHRES3=0 VHYST3=0  
+*
+.PARAM TDELLH = {IF ( (DELAYLH < 1E-9) , 1E-9, DELAYLH ) } 
+.PARAM TDELHL = {IF ( (DELAYHL < 1E-9) , 1E-9, DELAYHL ) } 
+.PARAM RO = {IF ( (TDEL > 1E-15) & (ROUT < 1), 1, ROUT ) } 
+.PARAM TDEL = {(TDELLH+TDELHL)/2}
+.PARAM COUT={TDEL/(0.693*(RO+1U))}
+.PARAM VREFN = {(15-VTOHN)}
+.PARAM VREFP = {(15-VTOHP)}
+.PARAM RDELLH = {TDELLH/(0.693*(COUT+1F))*VREFP}
+.PARAM RDELHL = {TDELHL/(0.693*(COUT+1F))*VREFN}
+*
+EOUT OUT GND VALUE= { IF ( (V(IN1+,IN1-) > {VTHRES1}) | (V(IN2+,IN2-) > {VTHRES2}) | (V(IN3+,IN3-) > {VTHRES3}), 
++ VOUTL + RDELLH*I(EOUT)*V(1,GND), VOUTH + RDELHL*I(EOUT)*V(1,GND) ) }
+E1 1 GND VALUE= { IF ( (V(VCC,GND) > {VTOHP+0.01}), 1/(V(VCC,GND)-VTOHP), 100 ) }
+COUT OUT GND {COUT}
+.ENDS COMP3INPNORSD
+
+.SUBCKT 1N4148 1 2
+D1          1 2  D_1N4148_1
+.MODEL D_1N4148_1 D( IS=1N N=1.7 BV=75 IBV=5U RS=2M 
++      CJO=4P VJ=750M M=330M FC=500M TT=25.9N 
++      EG=1.11 XTI=3 KF=0 AF=1 )
+.ENDS
+
+.PARAM LS = 1.0U
+.PARAM VTOP_ = 0.31
+.PARAM VTOP = 0.14
+.PARAM VTON = 0.14
+.PARAM VTOMP = 0.6
+.PARAM VTOMN = 0.55
+.PARAM VTOHP = 0.85
+.PARAM VTOHN = 0.80
+.PARAM LAMBDA = 2M
+.PARAM KPN = 6.0E-05
+.PARAM KPP = 3.0E-05
+.PARAM LDN = 0.07U
+.PARAM LDP = 0.07U
+.PARAM RSW = 1810
+.PARAM RSN = 1.41
+.PARAM VBMUL = 1E6
+.PARAM RPAR = 1T
+.PARAM CBDJ = 1 
+.PARAM CBDS = 1 
+.PARAM CN = 0.8
+*0.8U
+.PARAM CJN = {CN*180U}
+.PARAM CJP = {CN*300U} 
+.PARAM CJSWN = {CN*1N}
+.PARAM CJSWP = {CN*2.2N}
+.PARAM XJN = 0.2U
+.PARAM CGSON = {CN*0.6 * XJN * COX} 
+.PARAM CGDON = {CGSON}
+.PARAM XJP = 0.3U
+.PARAM CGSOP = {CN*0.6 * XJN * COX} 
+.PARAM CGDOP = {CGSOP}
+.PARAM EPSSIO2 = {3.9*8.854214871E-12}
+.PARAM TOX = 1000E-10
+.PARAM COX = {EPSSIO2/TOX}
+.PARAM EC = 1.5E6
+.PARAM VTOCP = {VTOHP+0.05}
+.PARAM VTOCN = {VTOHN+0.05}
+*CG
+.PARAM CCG = 0.2
+.PARAM CJNCG = {CCG*180U}
+.PARAM CJPCG = {CCG*300U} 
+.PARAM CJSWNCG = {CCG*1N}
+.PARAM CJSWPCG = {CCG*2.2N}
+.PARAM XJNCG = 0.2U
+.PARAM CGSONCG = {CCG*0.6 * XJNCG * COXCG} 
+.PARAM CGDONCG = {CGSONCG}
+.PARAM XJPCG = 0.3U
+.PARAM CGSOPCG = {CCG*0.6 * XJNCG * COXCG} 
+.PARAM CGDOPCG = {CGSOPCG}
+.PARAM TOXCG = 1000E-10
+.PARAM COXCG = {EPSSIO2/TOXCG}
\ No newline at end of file
diff --git a/examples/probe/VDMOS_models.lib b/examples/probe/VDMOS_models.lib
new file mode 100644
index 000000000..b53103398
--- /dev/null
+++ b/examples/probe/VDMOS_models.lib
@@ -0,0 +1,20 @@
+.model IRFP240 VDMOS nchan
++ Vto=4 Kp=5.9 Lambda=.001 Theta=0.015 ksubthres=.27
++ Rd=61m Rs=18m Rg=3 Rds=1e7
++ Cgdmax=2.45n Cgdmin=10p a=0.3 Cgs=1.2n
++ Is=60p N=1.1 Rb=14m XTI=3
++ Cjo=1.5n Vj=0.8 m=0.5
++ tcvth=0.0065 MU=-1.27 texp0=1.5
++ Rthjc=0.4 Cthj=0.1
++ mtriode=0.8
+
+.model IRFP9240 VDMOS pchan
++ Vto=-4 Kp=8.8 Lambda=.003 Theta=0.08 ksubthres=.35
++ Rd=180m Rs=50m Rg=3 Rds=1e7
++ Cgdmax=1.25n Cgdmin=50p a=0.23 Cgs=1.15n
++ Is=150p N=1.3 Rb=16m XTI=2
++ Cjo=1.3n Vj=0.8 m=0.5
++ tcvth=0.004 MU=-1.27 texp0=1.5
++ Rthjc=0.4 Cthj=0.1
++ mtriode=0.6
++ tnom=29
diff --git a/examples/probe/ac-test.cir b/examples/probe/ac-test.cir
new file mode 100644
index 000000000..627d9735b
--- /dev/null
+++ b/examples/probe/ac-test.cir
@@ -0,0 +1,20 @@
+.probe test with ac
+
+V1 1 0 dc 0 ac 1
+R1 1 2 1k 
+R2 2 3 1k
+R3 3 0 1k
+C2 2 3 1u
+C3 3 0 1u
+
+.ac dec 5 10 10000
+
+.probe i(R2) vd(R2) vd(R3) v(2)
+
+.control
+run
+display
+print vd_r2/i(r2)
+plot mag(vd_r3)
+.endc
+.end
diff --git a/examples/probe/mos-test.cir b/examples/probe/mos-test.cir
new file mode 100644
index 000000000..32b1622c7
--- /dev/null
+++ b/examples/probe/mos-test.cir
@@ -0,0 +1,35 @@
+.probe test with simple CMOS inverter
+
+Vd dd 0 dc 5
+Vin in 0 dc 0 PULSE (0 5 0 10n 10n 100n 200n)
+Vs ss 0 dc 0
+
+
+mn1 out in ss ss nm
+mp1 out in dd dd pm
+.model nm nmos
+.model pm pmos
+
+*.dc vin 0 5 0.1
+.tran 5n 500n
+
+* inputs o.k.
+.probe i(mp1:s) i(mn1:s) v(in) v(out) vd(mn1:d:s) vd(mp1:1, mn1:1)
+
+* buggy inputs
+.probe i(mn1:z) vd(mp1:0:0) vd(mp1:1:1) hhhh) i(:u) VD(z) i(())
+
+.save @mn1[id]
+
+.control
+run
+display
+set xbrushwidth=2
+*plot commands o.k.
+plot i(mn1:s) i(mp1:s)
+*buggy plot commands
+plot i(mp1:8)
+plot in out
+plot  @mn1[id] - i(mn1:s)
+.endc
+.end