From cd1b8e06da09daf5b2b9c359593bbb37496a9b96 Mon Sep 17 00:00:00 2001
From: Holger Vogt <holger.vogt@uni-due.de>
Date: Sat, 10 Mar 2018 16:36:43 +0100
Subject: [PATCH] examples/adms/bsimbulk, adapt to ngspice syntax

---
 examples/adms/bsimbulk/gummel_nmos.sp |  4 ++--
 examples/adms/bsimbulk/gummel_pmos.sp | 21 +++++++++++++--------
 examples/adms/bsimbulk/idvd_nmos.sp   | 12 +++++++-----
 examples/adms/bsimbulk/idvd_pmos.sp   | 14 ++++++++------
 examples/adms/bsimbulk/idvg_nmos.sp   | 18 ++++++++++++------
 examples/adms/bsimbulk/idvg_pmos.sp   | 18 ++++++++++++------
 examples/adms/bsimbulk/inv_dc.sp      | 12 ++++++++----
 examples/adms/bsimbulk/inv_tran.sp    | 10 +++++++---
 examples/adms/bsimbulk/model.l        |  6 ++++--
 examples/adms/bsimbulk/ring_osc.sp    | 19 ++++++++++++-------
 10 files changed, 85 insertions(+), 49 deletions(-)

diff --git a/examples/adms/bsimbulk/gummel_nmos.sp b/examples/adms/bsimbulk/gummel_nmos.sp
index 0843da1d1..11c3fb698 100644
--- a/examples/adms/bsimbulk/gummel_nmos.sp
+++ b/examples/adms/bsimbulk/gummel_nmos.sp
@@ -3,7 +3,7 @@
 .option post ingold numdgt=10
 .temp 27
 
-.hdl "bsimbulk.va"
+*.hdl "bsimbulk.va"
 .include "model.l"
 
 vd d 0 dc=0
@@ -11,7 +11,7 @@ vg g 0 dc=1.0
 es s 0 d 0 -1
 vb b 0 dc=0
 
-x1 d g s b nch W=10u L=10u
+m1 d g s b nch W=10u L=10u
 
 .dc vd -0.1 0.1 0.001 vg 0.0 1.0 0.2
 .probe dc ids=par'-i(vd)'
diff --git a/examples/adms/bsimbulk/gummel_pmos.sp b/examples/adms/bsimbulk/gummel_pmos.sp
index 227d66d6d..1334ebc64 100644
--- a/examples/adms/bsimbulk/gummel_pmos.sp
+++ b/examples/adms/bsimbulk/gummel_pmos.sp
@@ -3,7 +3,7 @@
 .option post ingold numdgt=10
 .temp 27
 
-.hdl "bsimbulk.va"
+*.hdl "bsimbulk.va"
 .include "model.l"
 
 vd d 0 dc=0
@@ -11,13 +11,18 @@ vg g 0 dc=-0.5
 es s 0 d 0 -1
 vb b 0 dc=0
 
-x1 d g s b pch W=10e-6 L=10e-6
+m1 d g s b pch W=10e-6 L=10e-6
 
-.dc vd -0.1 0.1 0.001 vg -1 -0.4 -0.3
-.probe dc ids=par'-i(vd)'
-.probe dc gx=deriv(ids)
-.probe dc gx2=deriv(gx)
-.probe dc gx3=deriv(gx2)
-.print dc par'ids' par'gx' par'gx2' par'gx3'
+.dc vd -0.1 0.1 0.001 vg -1 -0.4 0.3
+*.probe dc ids=par'-i(vd)'
+*.probe dc gx=deriv(ids)
+*.probe dc gx2=deriv(gx)
+*.probe dc gx3=deriv(gx2)
+*.print dc par'ids' par'gx' par'gx2' par'gx3'
+
+.control
+run
+plot i(es)
+.endc
 
 .end
diff --git a/examples/adms/bsimbulk/idvd_nmos.sp b/examples/adms/bsimbulk/idvd_nmos.sp
index c27e19eab..b59194d8e 100644
--- a/examples/adms/bsimbulk/idvd_nmos.sp
+++ b/examples/adms/bsimbulk/idvd_nmos.sp
@@ -3,7 +3,7 @@
 .option post ingold numdgt=10
 .temp 27
 
-.hdl "bsimbulk.va"
+*.hdl "bsimbulk.va"
 .include "model.l"
 
 vd d 0 dc=1.3
@@ -11,11 +11,13 @@ vg g 0 dc=0
 vs s 0 dc=0
 vb b 0 dc=0
 
-x1 d g s b nch W=10e-6 L=10e-6
+m1 d g s b nch W=10e-6 L=10e-6
 
 .dc vd 0.0 1.3 0.01 vg 0.4 1 0.3
-.probe dc ids=par'-i(vd)'
-.probe dc gds=deriv(ids)
-.print dc par'ids' par'gds'
+
+.control
+run
+plot i(vs)
+.endc
 
 .end
diff --git a/examples/adms/bsimbulk/idvd_pmos.sp b/examples/adms/bsimbulk/idvd_pmos.sp
index 3820fdeda..b35d0363e 100644
--- a/examples/adms/bsimbulk/idvd_pmos.sp
+++ b/examples/adms/bsimbulk/idvd_pmos.sp
@@ -3,7 +3,7 @@
 .option post ingold numdgt=10
 .temp 27
 
-.hdl "bsimbulk.va"
+*.hdl "bsimbulk.va"
 .include "model.l"
 
 vd d 0 dc=-1
@@ -11,11 +11,13 @@ vg g 0 dc=0
 vs s 0 dc=0
 vb b 0 dc=0
 
-x1 d g s b pch W=10e-6 L=10e-6
+m1 d g s b pch W=10e-6 L=10e-6
 
-.dc vd -1.3 0.0 0.01 vg -1 -0.4 -0.3
-.probe dc ids=par'i(vd)'
-.probe dc gds=deriv(ids)
-.print dc par'ids' par'gds'
+.dc vd -1.3 0.0 0.01 vg -1 -0.4 0.3
+
+.control
+run
+plot i(vs)
+.endc
 
 .end
diff --git a/examples/adms/bsimbulk/idvg_nmos.sp b/examples/adms/bsimbulk/idvg_nmos.sp
index b169adc37..cbacc496b 100644
--- a/examples/adms/bsimbulk/idvg_nmos.sp
+++ b/examples/adms/bsimbulk/idvg_nmos.sp
@@ -3,7 +3,7 @@
 .option post ingold numdgt=10
 .temp 27
 
-.hdl "bsimbulk.va"
+*.hdl "bsimbulk.va"
 .include "model.l"
 
 vd d 0 dc=0.05
@@ -11,12 +11,18 @@ vg g 0 dc=0
 vs s 0 dc=0
 vb b 0 dc=0
 
-x1 d g s b nch W=10e-6 L=10e-6
+m1 d g s b nch W=10e-6 L=10e-6
 
 .dc vg -1.3 1.3 0.01 vb -0.3 0 0.1
-.probe dc ids=par'-i(vd)'
-.probe dc gm=deriv(ids)
-.probe dc gm2=deriv(gm)
-.print dc par'ids' par'gm' par'gm2'
+*.probe dc ids=par'-i(vd)'
+*.probe dc gm=deriv(ids)
+*.probe dc gm2=deriv(gm)
+*.print dc par'ids' par'gm' par'gm2'
+
+
+.control
+run
+plot i(vs)
+.endc
 
 .end
diff --git a/examples/adms/bsimbulk/idvg_pmos.sp b/examples/adms/bsimbulk/idvg_pmos.sp
index 6caa57871..e9ed0b510 100644
--- a/examples/adms/bsimbulk/idvg_pmos.sp
+++ b/examples/adms/bsimbulk/idvg_pmos.sp
@@ -3,7 +3,7 @@
 .option post ingold numdgt=10
 .temp 27
 
-.hdl "bsimbulk.va"
+*.hdl "bsimbulk.va"
 .include "model.l"
 
 vd d 0 dc=-0.05
@@ -11,12 +11,18 @@ vg g 0 dc=0
 vs s 0 dc=0
 vb b 0 dc=0
 
-x1 d g s b pch W=10e-6 L=10e-6
+m1 d g s b pch W=10e-6 L=10e-6
 
 .dc vg -1.3.0 1.3 0.01 vb 0 -0.3 -0.1
-.probe dc ids=par'i(vd)'
-.probe dc gm=deriv(ids)
-.probe dc gm2=deriv(gm)
-.print dc par'ids' par'gm' par'gm2'
+*.probe dc ids=par'i(vd)'
+*.probe dc gm=deriv(ids)
+*.probe dc gm2=deriv(gm)
+*.print dc par'ids' par'gm' par'gm2'
+
+
+.control
+run
+plot i(vs)
+.endc
 
 .end
diff --git a/examples/adms/bsimbulk/inv_dc.sp b/examples/adms/bsimbulk/inv_dc.sp
index a9d1967f1..fc7466f83 100644
--- a/examples/adms/bsimbulk/inv_dc.sp
+++ b/examples/adms/bsimbulk/inv_dc.sp
@@ -3,20 +3,24 @@
 .option post ingold numdgt=10
 .temp 27
 
-.hdl "bsimbulk.va"
+*.hdl "bsimbulk.va"
 .include "model.l"
 
 v1 vdd 0 dc=1.0
 v2 in 0 dc=0.5
 
 .subckt inv vin vout vdd vss
-    xn vout vin vss vss nch W=10u L=10u
-    xp vout vin vdd vdd pch W=10u L=10u
+    mn vout vin vss vss nch W=10u L=10u
+    mp vout vin vdd vdd pch W=10u L=10u
 .ends
 
 x1 in out vdd 0 inv
 
 .dc v2 0 1 0.01
-.print dc v(in) v(out)
+
+.control
+run
+plot v(in) v(out)
+.endc
 
 .end
diff --git a/examples/adms/bsimbulk/inv_tran.sp b/examples/adms/bsimbulk/inv_tran.sp
index dc69e682e..de8435d93 100644
--- a/examples/adms/bsimbulk/inv_tran.sp
+++ b/examples/adms/bsimbulk/inv_tran.sp
@@ -10,8 +10,8 @@ v1 vdd 0 dc=1.0
 v2 in 0 dc=0.5 sin(0.5 0.5 1meg)
 
 .subckt inv vin vout vdd vss
-    xn vout vin vss vss nch W=10u L=10u
-    xp vout vin vdd vdd pch W=10u L=10u
+    mn vout vin vss vss nch W=10u L=10u
+    mp vout vin vdd vdd pch W=10u L=10u
 .ends
 
 x1 in 1 vdd 0 inv
@@ -21,6 +21,10 @@ x4 3 4 vdd 0 inv
 x5 4 out vdd 0 inv
 
 .tran 10n 5u
-.print tran v(in) v(out)
+
+.control
+run
+plot v(in) v(out)
+.endc
 
 .end
diff --git a/examples/adms/bsimbulk/model.l b/examples/adms/bsimbulk/model.l
index 2fd9050b1..070c0d21e 100644
--- a/examples/adms/bsimbulk/model.l
+++ b/examples/adms/bsimbulk/model.l
@@ -1,4 +1,5 @@
-.model nch bsimbulk
+.model nch NMOS
++level=77
 +TYPE = 1
 +GEOMOD = 0
 +RGEOMOD = 0
@@ -210,7 +211,8 @@
 +SCC = 0
 +SC = 0
 
-.model pch bsimbulk
+.model pch PMOS
++level=77
 +TYPE = -1
 +GEOMOD = 0
 +RGEOMOD = 0
diff --git a/examples/adms/bsimbulk/ring_osc.sp b/examples/adms/bsimbulk/ring_osc.sp
index c8e9269b3..82083c64b 100644
--- a/examples/adms/bsimbulk/ring_osc.sp
+++ b/examples/adms/bsimbulk/ring_osc.sp
@@ -1,15 +1,15 @@
 * Sample netlist: 17-stage ring oscillator *
 
-.options post ingold numdgt=10 dcon=1
+.options abstol=1e-6 reltol=1e-6
 
-.hdl "bsimbulk.va"
+*.hdl "bsimbulk.va"
 .include "model.l"
 
 v1 vdd 0 dc=1.0
 
 .subckt inv vin vout vdd vss
-    xn vout vin vss vss nch W=10e-6 L=10e-6
-    xp vout vin vdd vdd pch W=10e-6 L=10e-6
+    mn vout vin vss vss nch W=10e-6 L=10e-6
+    mp vout vin vdd vdd pch W=10e-6 L=10e-6
 .ends
 
 x1 1 2 vdd 0 inv
@@ -30,13 +30,18 @@ x15 15 16 vdd 0 inv
 x16 16 17 vdd 0 inv
 x17 17 1 vdd 0 inv
 
-.ic 1=1
+*.ic 1=1
 
 .tran 1n 10u
 .print tran v(1)
 .measure tran t1 when v(1)=0.5 cross=1
 .measure tran t2 when v(1)=0.5 cross=7
-.measure tran period param'(t2-t1)/3'
-.measure tran delay_per_stage param'period/34'
+*.measure tran period param'(t2-t1)/3'
+*.measure tran delay_per_stage param'period/34'
+
+.control
+run
+plot v(1)
+.endc
 
 .end