diff --git a/src/maths/ni/niaciter.c b/src/maths/ni/niaciter.c index eccac93a0..0b14ddd08 100644 --- a/src/maths/ni/niaciter.c +++ b/src/maths/ni/niaciter.c @@ -47,6 +47,14 @@ retry: /* either singular equations or no memory, in either case, * let caller handle problem */ + + int i, j ; + SMPgetError(ckt->CKTmatrix, &i, &j); + if(eq(NODENAME(ckt, i), NODENAME(ckt, j))) + SPfrontEnd->IFerrorf(ERR_WARNING, "singular matrix: check node %s\n", NODENAME(ckt, i)); + else + SPfrontEnd->IFerrorf(ERR_WARNING, "singular matrix: check nodes %s and %s\n", NODENAME(ckt, i), NODENAME(ckt, j)); + return(error); } } @@ -61,6 +69,14 @@ retry: * current LU factorization. Maybe if we reload and * try to reorder again it will help... */ + + int i, j ; + SMPgetError(ckt->CKTmatrix, &i, &j); + if(eq(NODENAME(ckt, i), NODENAME(ckt, j))) + SPfrontEnd->IFerrorf(ERR_WARNING, "singular matrix: check node %s\n", NODENAME(ckt, i)); + else + SPfrontEnd->IFerrorf(ERR_WARNING, "singular matrix: check nodes %s and %s\n", NODENAME(ckt, i), NODENAME(ckt, j)); + ckt->CKTniState |= NIACSHOULDREORDER; goto retry; } diff --git a/src/spicelib/devices/vsrc/vsrcbindCSC.c b/src/spicelib/devices/vsrc/vsrcbindCSC.c index 38c122f8a..142f0b6a8 100644 --- a/src/spicelib/devices/vsrc/vsrcbindCSC.c +++ b/src/spicelib/devices/vsrc/vsrcbindCSC.c @@ -25,10 +25,33 @@ VSRCbindCSC (GENmodel *inModel, CKTcircuit *ckt) /* loop through all the instances of the model */ for (here = VSRCinstances(model); here != NULL ; here = VSRCnextInstance(here)) { + +#ifdef RFSPICE + if (here->VSRCisPort) + { + CREATE_KLU_BINDING_TABLE(VSRCposPosPtr, VSRCposPosBinding, VSRCposNode, VSRCposNode); + CREATE_KLU_BINDING_TABLE(VSRCnegNegPtr, VSRCresResBinding, VSRCresNode, VSRCresNode); + CREATE_KLU_BINDING_TABLE(VSRCposNegPtr, VSRCposResBinding, VSRCposNode, VSRCresNode); + CREATE_KLU_BINDING_TABLE(VSRCnegPosPtr, VSRCresPosBinding, VSRCresNode, VSRCposNode); + + CREATE_KLU_BINDING_TABLE(VSRCposIbrPtr, VSRCposIbrBinding, VSRCresNode, VSRCbranch); + CREATE_KLU_BINDING_TABLE(VSRCnegIbrPtr, VSRCnegIbrBinding, VSRCnegNode, VSRCbranch); + CREATE_KLU_BINDING_TABLE(VSRCibrNegPtr, VSRCibrNegBinding, VSRCbranch, VSRCnegNode); + CREATE_KLU_BINDING_TABLE(VSRCibrPosPtr, VSRCibrPosBinding, VSRCbranch, VSRCresNode); + } + else + { + CREATE_KLU_BINDING_TABLE(VSRCposIbrPtr, VSRCposIbrBinding, VSRCposNode, VSRCbranch); + CREATE_KLU_BINDING_TABLE(VSRCnegIbrPtr, VSRCnegIbrBinding, VSRCnegNode, VSRCbranch); + CREATE_KLU_BINDING_TABLE(VSRCibrNegPtr, VSRCibrNegBinding, VSRCbranch, VSRCnegNode); + CREATE_KLU_BINDING_TABLE(VSRCibrPosPtr, VSRCibrPosBinding, VSRCbranch, VSRCposNode); + } +#else CREATE_KLU_BINDING_TABLE(VSRCposIbrPtr, VSRCposIbrBinding, VSRCposNode, VSRCbranch); CREATE_KLU_BINDING_TABLE(VSRCnegIbrPtr, VSRCnegIbrBinding, VSRCnegNode, VSRCbranch); CREATE_KLU_BINDING_TABLE(VSRCibrNegPtr, VSRCibrNegBinding, VSRCbranch, VSRCnegNode); CREATE_KLU_BINDING_TABLE(VSRCibrPosPtr, VSRCibrPosBinding, VSRCbranch, VSRCposNode); +#endif /* Pole-Zero Analysis */ if (here->VSRCibrIbrPtr) @@ -63,10 +86,34 @@ VSRCbindCSCComplex (GENmodel *inModel, CKTcircuit *ckt) /* loop through all the instances of the model */ for (here = VSRCinstances(model); here != NULL ; here = VSRCnextInstance(here)) { + +#ifdef RFSPICE + if (here->VSRCisPort) + { + CONVERT_KLU_BINDING_TABLE_TO_COMPLEX(VSRCposPosPtr, VSRCposPosBinding, VSRCposNode, VSRCposNode); + CONVERT_KLU_BINDING_TABLE_TO_COMPLEX(VSRCnegNegPtr, VSRCresResBinding, VSRCresNode, VSRCresNode); + CONVERT_KLU_BINDING_TABLE_TO_COMPLEX(VSRCposNegPtr, VSRCposResBinding, VSRCposNode, VSRCresNode); + CONVERT_KLU_BINDING_TABLE_TO_COMPLEX(VSRCnegPosPtr, VSRCresPosBinding, VSRCresNode, VSRCposNode); + + CONVERT_KLU_BINDING_TABLE_TO_COMPLEX(VSRCposIbrPtr, VSRCposIbrBinding, VSRCresNode, VSRCbranch); + CONVERT_KLU_BINDING_TABLE_TO_COMPLEX(VSRCnegIbrPtr, VSRCnegIbrBinding, VSRCnegNode, VSRCbranch); + CONVERT_KLU_BINDING_TABLE_TO_COMPLEX(VSRCibrNegPtr, VSRCibrNegBinding, VSRCbranch, VSRCnegNode); + CONVERT_KLU_BINDING_TABLE_TO_COMPLEX(VSRCibrPosPtr, VSRCibrPosBinding, VSRCbranch, VSRCresNode); + } + else + { + CONVERT_KLU_BINDING_TABLE_TO_COMPLEX(VSRCposIbrPtr, VSRCposIbrBinding, VSRCposNode, VSRCbranch); + CONVERT_KLU_BINDING_TABLE_TO_COMPLEX(VSRCnegIbrPtr, VSRCnegIbrBinding, VSRCnegNode, VSRCbranch); + CONVERT_KLU_BINDING_TABLE_TO_COMPLEX(VSRCibrNegPtr, VSRCibrNegBinding, VSRCbranch, VSRCnegNode); + CONVERT_KLU_BINDING_TABLE_TO_COMPLEX(VSRCibrPosPtr, VSRCibrPosBinding, VSRCbranch, VSRCposNode); + } +#else CONVERT_KLU_BINDING_TABLE_TO_COMPLEX(VSRCposIbrPtr, VSRCposIbrBinding, VSRCposNode, VSRCbranch); CONVERT_KLU_BINDING_TABLE_TO_COMPLEX(VSRCnegIbrPtr, VSRCnegIbrBinding, VSRCnegNode, VSRCbranch); CONVERT_KLU_BINDING_TABLE_TO_COMPLEX(VSRCibrNegPtr, VSRCibrNegBinding, VSRCbranch, VSRCnegNode); CONVERT_KLU_BINDING_TABLE_TO_COMPLEX(VSRCibrPosPtr, VSRCibrPosBinding, VSRCbranch, VSRCposNode); +#endif + /* Pole-Zero Analysis */ if ((here-> VSRCbranch != 0) && (here-> VSRCbranch != 0)) { @@ -95,10 +142,34 @@ VSRCbindCSCComplexToReal (GENmodel *inModel, CKTcircuit *ckt) /* loop through all the instances of the model */ for (here = VSRCinstances(model); here != NULL ; here = VSRCnextInstance(here)) { + +#ifdef RFSPICE + if (here->VSRCisPort) + { + CONVERT_KLU_BINDING_TABLE_TO_REAL(VSRCposPosPtr, VSRCposPosBinding, VSRCposNode, VSRCposNode); + CONVERT_KLU_BINDING_TABLE_TO_REAL(VSRCnegNegPtr, VSRCresResBinding, VSRCresNode, VSRCresNode); + CONVERT_KLU_BINDING_TABLE_TO_REAL(VSRCposNegPtr, VSRCposResBinding, VSRCposNode, VSRCresNode); + CONVERT_KLU_BINDING_TABLE_TO_REAL(VSRCnegPosPtr, VSRCresPosBinding, VSRCresNode, VSRCposNode); + + CONVERT_KLU_BINDING_TABLE_TO_REAL(VSRCposIbrPtr, VSRCposIbrBinding, VSRCresNode, VSRCbranch); + CONVERT_KLU_BINDING_TABLE_TO_REAL(VSRCnegIbrPtr, VSRCnegIbrBinding, VSRCnegNode, VSRCbranch); + CONVERT_KLU_BINDING_TABLE_TO_REAL(VSRCibrNegPtr, VSRCibrNegBinding, VSRCbranch, VSRCnegNode); + CONVERT_KLU_BINDING_TABLE_TO_REAL(VSRCibrPosPtr, VSRCibrPosBinding, VSRCbranch, VSRCresNode); + } + else + { + CONVERT_KLU_BINDING_TABLE_TO_REAL(VSRCposIbrPtr, VSRCposIbrBinding, VSRCposNode, VSRCbranch); + CONVERT_KLU_BINDING_TABLE_TO_REAL(VSRCnegIbrPtr, VSRCnegIbrBinding, VSRCnegNode, VSRCbranch); + CONVERT_KLU_BINDING_TABLE_TO_REAL(VSRCibrNegPtr, VSRCibrNegBinding, VSRCbranch, VSRCnegNode); + CONVERT_KLU_BINDING_TABLE_TO_REAL(VSRCibrPosPtr, VSRCibrPosBinding, VSRCbranch, VSRCposNode); + } +#else CONVERT_KLU_BINDING_TABLE_TO_REAL(VSRCposIbrPtr, VSRCposIbrBinding, VSRCposNode, VSRCbranch); CONVERT_KLU_BINDING_TABLE_TO_REAL(VSRCnegIbrPtr, VSRCnegIbrBinding, VSRCnegNode, VSRCbranch); CONVERT_KLU_BINDING_TABLE_TO_REAL(VSRCibrNegPtr, VSRCibrNegBinding, VSRCbranch, VSRCnegNode); CONVERT_KLU_BINDING_TABLE_TO_REAL(VSRCibrPosPtr, VSRCibrPosBinding, VSRCbranch, VSRCposNode); +#endif + /* Pole-Zero Analysis */ if ((here-> VSRCbranch != 0) && (here-> VSRCbranch != 0)) { diff --git a/src/spicelib/devices/vsrc/vsrcdefs.h b/src/spicelib/devices/vsrc/vsrcdefs.h index 2ab796fe5..9f5786c1d 100644 --- a/src/spicelib/devices/vsrc/vsrcdefs.h +++ b/src/spicelib/devices/vsrc/vsrcdefs.h @@ -117,6 +117,13 @@ typedef struct sVSRCinstance { BindElement *VSRCibrNegBinding ; BindElement *VSRCibrPosBinding ; BindElement *VSRCibrIbrBinding ; + +#ifdef RFSPICE + BindElement *VSRCposPosBinding ; + BindElement *VSRCresResBinding ; + BindElement *VSRCposResBinding ; + BindElement *VSRCresPosBinding ; +#endif #endif } VSRCinstance ; diff --git a/src/spicelib/devices/vsrc/vsrcload.c b/src/spicelib/devices/vsrc/vsrcload.c index c68138eb1..a93687087 100644 --- a/src/spicelib/devices/vsrc/vsrcload.c +++ b/src/spicelib/devices/vsrc/vsrcload.c @@ -42,7 +42,7 @@ VSRCload(GENmodel *inModel, CKTcircuit *ckt) here=VSRCnextInstance(here)) { #ifndef RFSPICE - * (here->VSRCposIbrPtr) += 1.0; + *(here->VSRCposIbrPtr) += 1.0; *(here->VSRCnegIbrPtr) -= 1.0; *(here->VSRCibrPosPtr) += 1.0; *(here->VSRCibrNegPtr) -= 1.0;