From c757dbdd2b3602f2af7001ae66e397049428efee Mon Sep 17 00:00:00 2001 From: rlar Date: Sun, 30 Jul 2017 17:59:39 +0200 Subject: [PATCH] bsimcmg, LSP issue LSP is declared to be a "module" parameter, yet has a default value which is calculated from a "instance" parameter "L" and a "model" parameter "XL" which necessairly means, LSP is a "instance" parameter. to avoid excessive divertion from the original source, we use a local variable "LSP_i" which is set either to the default value calculated from XL and L, or to the user specified "LSP" model parameter --- bsimcmg_benchmark_test/gummel_n.sp | 2 -- .../adms/bsimcmg/admsva/bsimcmg_body.include | 20 ++++++++++++------- 2 files changed, 13 insertions(+), 9 deletions(-) diff --git a/bsimcmg_benchmark_test/gummel_n.sp b/bsimcmg_benchmark_test/gummel_n.sp index b37d417b1..239294e5d 100644 --- a/bsimcmg_benchmark_test/gummel_n.sp +++ b/bsimcmg_benchmark_test/gummel_n.sp @@ -14,8 +14,6 @@ vbulk bulk 0 dc=0.0 * --- Transistor --- -* FIXME, parameter LSP has a different default !! -* see commit for bsimcmg_body.include m1 drain gate source bulk 0 nmos1 TFIN=15n L=30n NFIN=10 NRS=1 NRD=1 + FPITCH = 4.00E-08 diff --git a/src/spicelib/devices/adms/bsimcmg/admsva/bsimcmg_body.include b/src/spicelib/devices/adms/bsimcmg/admsva/bsimcmg_body.include index 9cf33ad6a..54aff60ac 100644 --- a/src/spicelib/devices/adms/bsimcmg/admsva/bsimcmg_body.include +++ b/src/spicelib/devices/adms/bsimcmg/admsva/bsimcmg_body.include @@ -381,7 +381,7 @@ `MPRcc( CRATIO ,0.5 ,"" ,0.0 ,1.0 ,"Ratio of the corner area filled with silicon to the total corner area" ) `MPRoo( DELTAPRSD ,0.0 ,"m" ,-FPITCH ,inf ,"Change in silicon/silicide interface length due to non-rectangular epi" ) `MPIcc( SDTERM ,0 ,"" ,0 ,1 ,"Indicator of whether the source/drain are terminated with silicide" ) -`MPRnb( LSP ,(0.2*(3.0e-8 + XL)) ,"m" ,"Thickness of the gate sidewall spacer" ) +`MPRnb( LSP ,-1 ,"m" ,"Thickness of the gate sidewall spacer" ) `MPRco( EPSRSP ,3.9 ,"" ,1.0 ,inf ,"Relative dielectric constant of the spacer" ) `MPRoz( TGATE ,3.0e-8 ,"m" ,"Gate height on top of the hard mask" ) `MPRcz( TMASK ,3.0e-8 ,"m" ,"Height of hard mask on top of the fin" ) @@ -986,6 +986,8 @@ real Cins, Ach, Weff_UFCM, qdep,rc, vth_fixed_factor_Sub, vth_fixed_factor_SI, q real fieldnormalizationfactor, auxQMfact, QMFACTORCVfinal; real psipclamp, sqrtpsip, nq, F0; +real LSP_i; + `Cfringe_2d_vars(); //=================================================== @@ -2224,6 +2226,10 @@ analog begin // Parasitic Source/Drain to Gate Fringe Capacitance Model if (CGEOMOD == 2) begin + if ($param_given(LSP)) + LSP_i = LSP; + else + LSP_i = 0.2*(L + XL); Hg = TGATE + TMASK; Trsd = 0.5 * (FPITCH - TFIN); Wg = max(0.0, Trsd - TOXP); @@ -2232,18 +2238,18 @@ analog begin // Top Component if (TMASK > 0.0) begin // Capacitance Model by Chung-Hsun Lin (IBM) - T0y = 3.467e-11 * `lln(1.0e-7 * EPSRSP / (3.9 * LSP)); - T1y = 0.942 * Hrsd * epssp / LSP; + T0y = 3.467e-11 * `lln(1.0e-7 * EPSRSP / (3.9 * LSP_i)); + T1y = 0.942 * Hrsd * epssp / LSP_i; Cgg_top = (T0y + T1y) * (TFIN + (FPITCH - TFIN) * CRATIO); end else begin - `Cfringe_2d(cfr_top_trigate, Hg, Hrsd, LSP, TFIN, LRSD, Lg, TOXP, 0.85, Cgg_top) + `Cfringe_2d(cfr_top_trigate, Hg, Hrsd, LSP_i, TFIN, LRSD, Lg, TOXP, 0.85, Cgg_top) end // Side Component if (TMASK > 0) begin - `Cfringe_2d(cfr_side_dblgate, Wg, Trsd, LSP, HFIN, LRSD, Lg, TOXP, 0.70, Cgg_side) + `Cfringe_2d(cfr_side_dblgate, Wg, Trsd, LSP_i, HFIN, LRSD, Lg, TOXP, 0.70, Cgg_side) end else begin - `Cfringe_2d(cfr_side_trigate, Wg, Trsd, LSP, HFIN, LRSD, Lg, TOXP, 0.85, Cgg_side) + `Cfringe_2d(cfr_side_trigate, Wg, Trsd, LSP_i, HFIN, LRSD, Lg, TOXP, 0.85, Cgg_side) end // Corner Component @@ -2256,7 +2262,7 @@ analog begin Acorner = (FPITCH - TFIN) * Hrsd; end end - Ccorner = (NFIN * Acorner + ARSDEND + ASILIEND) * epssp / LSP; + Ccorner = (NFIN * Acorner + ARSDEND + ASILIEND) * epssp / LSP_i; Cfr_geo = (Ccorner + Cgg_top * NFIN + CGEOE * Cgg_side * NFIN * 2.0) * NF; Cfr_geo = Cfr_geo * max(0.0, CGEOA + CGEOB * TFIN + CGEOC * FPITCH + CGEOD * LRSD); end