diff --git a/examples/digital/adder_behav.cir b/examples/digital/adder_behav.cir index 945c88e78..2ccadd76a 100644 --- a/examples/digital/adder_behav.cir +++ b/examples/digital/adder_behav.cir @@ -5,65 +5,6 @@ .include 74HCng_short_2.lib .param vcc=3 tripdt=6n -.SUBCKT ONEBIT 1 2 3 4 5 6 -* NODES: INPUT(2), CARRY-IN, OUTPUT, CARRY-OUT, VCC -X1 1 2 7 6 0 74HC00 -X2 1 7 8 6 0 74HC00 -X3 2 7 9 6 0 74HC00 -X4 8 9 10 6 0 74HC00 -X5 3 10 11 6 0 74HC00 -X6 3 11 12 6 0 74HC00 -X7 10 11 13 6 0 74HC00 -X8 12 13 4 6 0 74HC00 -X9 11 7 5 6 0 74HC00 -.ENDS ONEBIT - -.SUBCKT TWOBIT 1 2 3 4 5 6 7 8 9 -* NODES: INPUT - BIT0(2) / BIT1(2), OUTPUT - BIT0 / BIT1, -* CARRY-IN, CARRY-OUT, VCC -X1 1 2 7 5 10 9 ONEBIT -X2 3 4 10 6 8 9 ONEBIT -.ENDS TWOBIT - -.SUBCKT FOURBIT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 -* NODES: INPUT - BIT0(2) / BIT1(2) / BIT2(2) / BIT3(2), -* OUTPUT - BIT0 / BIT1 / BIT2 / BIT3, CARRY-IN, CARRY-OUT, VCC -X1 1 2 3 4 9 10 13 16 15 TWOBIT -X2 5 6 7 8 11 12 16 14 15 TWOBIT -.ENDS FOURBIT - -*** POWER -VCC 99 0 DC 3.3V - -*** ALL INPUTS -VIN1A 1 0 DC 0 PULSE(0 3 0 5NS 5NS 20NS 50NS) -VIN1B 2 0 DC 0 PULSE(0 3 0 5NS 5NS 30NS 100NS) -VIN2A 3 0 DC 0 PULSE(0 3 0 5NS 5NS 50NS 200NS) -VIN2B 4 0 DC 0 PULSE(0 3 0 5NS 5NS 90NS 400NS) -VIN3A 5 0 DC 0 PULSE(0 3 0 5NS 5NS 170NS 800NS) -VIN3B 6 0 DC 0 PULSE(0 3 0 5NS 5NS 330NS 1600NS) -VIN4A 7 0 DC 0 PULSE(0 3 0 5NS 5NS 650NS 3200NS) -VIN4B 8 0 DC 0 PULSE(0 3 0 5NS 5NS 1290NS 6400NS) - -*** DEFINE NOMINAL CIRCUIT -X1 1 2 3 4 5 6 7 8 9 10 11 12 0 13 99 FOURBIT - -.option noinit acct -.TRAN 500p 6400NS -* save inputs -.save V(1) V(2) V(3) V(4) V(5) V(6) V(7) V(8) - -.control -pre_set strict_errorhandling -unset ngdebug -*save outputs and specials -save x1.x1.x1.7 V(9) V(10) V(11) V(12) V(13) -run -rusage -* plot the inputs, use offset to plot on top of each other -plot v(1) v(2)+4 v(3)+8 v(4)+12 v(5)+16 v(6)+20 v(7)+24 v(8)+28 -* plot the outputs, use offset to plot on top of each other -plot v(9) v(10)+4 v(11)+8 v(12)+12 v(13)+16 -.endc +.include adder_common.inc .END diff --git a/examples/digital/adder_common.inc b/examples/digital/adder_common.inc new file mode 100644 index 000000000..63db76d23 --- /dev/null +++ b/examples/digital/adder_common.inc @@ -0,0 +1,62 @@ +* Shared netlist for several example circuits using XSPICE-based 74HC00 model + +.SUBCKT ONEBIT 1 2 3 4 5 6 +* NODES: INPUT(2), CARRY-IN, OUTPUT, CARRY-OUT, VCC +X1 1 2 7 6 0 74HC00 +X2 1 7 8 6 0 74HC00 +X3 2 7 9 6 0 74HC00 +X4 8 9 10 6 0 74HC00 +X5 3 10 11 6 0 74HC00 +X6 3 11 12 6 0 74HC00 +X7 10 11 13 6 0 74HC00 +X8 12 13 4 6 0 74HC00 +X9 11 7 5 6 0 74HC00 +.ENDS ONEBIT + +.SUBCKT TWOBIT 1 2 3 4 5 6 7 8 9 +* NODES: INPUT - BIT0(2) / BIT1(2), OUTPUT - BIT0 / BIT1, +* CARRY-IN, CARRY-OUT, VCC +X1 1 2 7 5 10 9 ONEBIT +X2 3 4 10 6 8 9 ONEBIT +.ENDS TWOBIT + +.SUBCKT FOURBIT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 +* NODES: INPUT - BIT0(2) / BIT1(2) / BIT2(2) / BIT3(2), +* OUTPUT - BIT0 / BIT1 / BIT2 / BIT3, CARRY-IN, CARRY-OUT, VCC +X1 1 2 3 4 9 10 13 16 15 TWOBIT +X2 5 6 7 8 11 12 16 14 15 TWOBIT +.ENDS FOURBIT + +*** POWER +VCC 99 0 DC 3.3V + +*** ALL INPUTS +VIN1A 1 0 DC 0 PULSE(0 3 0 5NS 5NS 20NS 50NS) +VIN1B 2 0 DC 0 PULSE(0 3 0 5NS 5NS 30NS 100NS) +VIN2A 3 0 DC 0 PULSE(0 3 0 5NS 5NS 50NS 200NS) +VIN2B 4 0 DC 0 PULSE(0 3 0 5NS 5NS 90NS 400NS) +VIN3A 5 0 DC 0 PULSE(0 3 0 5NS 5NS 170NS 800NS) +VIN3B 6 0 DC 0 PULSE(0 3 0 5NS 5NS 330NS 1600NS) +VIN4A 7 0 DC 0 PULSE(0 3 0 5NS 5NS 650NS 3200NS) +VIN4B 8 0 DC 0 PULSE(0 3 0 5NS 5NS 1290NS 6400NS) + +*** DEFINE NOMINAL CIRCUIT +X1 1 2 3 4 5 6 7 8 9 10 11 12 0 13 99 FOURBIT + +.option noinit acct +.TRAN 500p 6400NS +* save inputs +.save V(1) V(2) V(3) V(4) V(5) V(6) V(7) V(8) + +.control +pre_set strict_errorhandling +unset ngdebug +*save outputs and specials +save x1.x1.x1.7 V(9) V(10) V(11) V(12) V(13) +run +rusage +* plot the inputs, use offset to plot on top of each other +plot v(1) v(2)+4 v(3)+8 v(4)+12 v(5)+16 v(6)+20 v(7)+24 v(8)+28 +* plot the outputs, use offset to plot on top of each other +plot v(9) v(10)+4 v(11)+8 v(12)+12 v(13)+16 +.endc diff --git a/examples/digital/auto_bridge/74HCng_auto.lib b/examples/digital/auto_bridge/74HCng_auto.lib new file mode 100644 index 000000000..a2d572ff9 --- /dev/null +++ b/examples/digital/auto_bridge/74HCng_auto.lib @@ -0,0 +1,35 @@ +* 74hcng_auto.lib - simplified wrapper for XSPICE NAND gate +* +* derived from 74HCng_short_2.lib but using automatic D<->A bridges. +* derived from 74HCxxx Model libraray for LTSPICE from www.linear.com/software +* +* XSPICE gate models are used, with output to an analogue node. +* +* Delays are given for Vcc = 2V/4.5V/6V (HC) from the +* Philips data sheets. http://www.philipslogic.com +* +* Delays are given for Vcc = 2V/4.5V/6V . +* Used delay: Td = (Tpd-Tr/2)*(4.5-0.5)/(Vcc-0.5) +* The gate delay has to be set to tpd minus 3ns for the input filter +* and another minus 3ns for Trise/2 +* td1 = tpd - 3ns - 3ns +* + +.param vcc=5 tripdt=6n + +* +* 2-input NAND gate +* vcc 2 /4.5/5 /6 +* tpd 25n/9n/7n/7n +* tr 19n/7n / /6n +.SUBCKT 74HC00 in1 in2 out NVCC NVGND vcc1={vcc} tripdt1={tripdt} +.param td1={1e-9*(9-3-3)*4.0/(vcc1-0.5)} +.param Rout={60*4.0/(vcc1-0.5)} ; standard output driver +.param Rload=10k ; The bidi bridge analogue port is type 'g' and needs load + +a6 [in1 in2] dout nand1 +.model nand1 d_nand(rise_delay = {td1} fall_delay = {td1} ++ input_load = 0.5e-12) +Rout dout out {Rout} +Rload dout 0 {Rload} +.ends diff --git a/examples/digital/auto_bridge/adder_auto.cir b/examples/digital/auto_bridge/adder_auto.cir new file mode 100644 index 000000000..bb33edadc --- /dev/null +++ b/examples/digital/auto_bridge/adder_auto.cir @@ -0,0 +1,11 @@ + ADDER - 4 BIT ALL-74HC00-GATE BINARY ADDER WITH AUTOMATIC BRIDGING + * behavioral gate description + * Automatic A/D insertion +*** SUBCIRCUIT DEFINITIONS +.include 74HCng_auto.lib + +.param vcc=3 tripdt=6n + +.include ../adder_common.inc + +.END diff --git a/examples/digital/auto_bridge/adder_bidi.cir b/examples/digital/auto_bridge/adder_bidi.cir new file mode 100644 index 000000000..20b5b9239 --- /dev/null +++ b/examples/digital/auto_bridge/adder_bidi.cir @@ -0,0 +1,20 @@ + ADDER - 4 BIT ALL-74HC00-GATE BINARY ADDER WITH BIDIRECTIONAL BRIDGES + * behavioral gate description + * Automatic A/D insertion using bi-directional bridges + +* Override the default bridges and force use of the bidi_bridge. + +.control +pre_set auto_bridge_d_out = ++ ( ".model auto_bridge bidi_bridge(out_high=%g in_low='%g/2' in_high='%g/2' )" ++ "auto_bridge%d [ %s ] [ %s ] null auto_bridge" 1000 ) +pre_set auto_bridge_d_in = ( $auto_bridge_d_out ) +.endc + +*** SUBCIRCUIT DEFINITIONS +.include 74HCng_auto.lib +.param vcc=3 tripdt=6n + +.include ../adder_common.inc + +.END diff --git a/examples/digital/auto_bridge/adder_bidi2.cir b/examples/digital/auto_bridge/adder_bidi2.cir new file mode 100644 index 000000000..804b3d0a4 --- /dev/null +++ b/examples/digital/auto_bridge/adder_bidi2.cir @@ -0,0 +1,23 @@ + ADDER - 4 BIT ALL-74HC00-GATE BINARY ADDER WITH AUTOMATIC BRIDGING + * behavioral gate description + * Automatic A/D insertion using bi-directional bridges + +* Override the default bridges and force use of the bidi_bridges with +* directions pre-set. + +.control +pre_set auto_bridge_d_out = ++ ( ".model auto_bridge_out bidi_bridge(direction=0 out_high=%g)" ++ "auto_bridge_out%d [ %s ] [ %s ] null auto_bridge_out" ) +pre_set auto_bridge_d_in = ++ ( ".model auto_bridge_in bidi_bridge(direction=1 in_low='%g/2' in_high='%g/2')" ++ "auto_bridge_in%d [ %s ] [ %s ] null auto_bridge_in" ) +.endc + +*** SUBCIRCUIT DEFINITIONS +.include 74HCng_auto.lib +.param vcc=3 tripdt=6n + +.include ../adder_common.inc + +.END diff --git a/examples/digital/auto_bridge/adder_bidi3.cir b/examples/digital/auto_bridge/adder_bidi3.cir new file mode 100644 index 000000000..c11d228ce --- /dev/null +++ b/examples/digital/auto_bridge/adder_bidi3.cir @@ -0,0 +1,28 @@ + ADDER - 4 BIT ALL-74HC00-GATE BINARY ADDER WITH AUTOMATIC BRIDGING + * behavioral gate description + * Automatic A/D insertion using bi-directional bridges + +* Override the default bridges and force use of the bidi_bridges with +* directions controlled by inputs. + +.control +pre_set auto_bridge_d_out = ++ ( ".model auto_bridge_out bidi_bridge(out_high=%g)" ++ "auto_bridge_out%d [ %s ] [ %s ] [ force_out ] auto_bridge_out" 1 ) +pre_set auto_bridge_d_in = ++ ( ".model auto_bridge_in bidi_bridge(in_low='%g/2' in_high='%g/2')" ++ "auto_bridge_in%d [ %s ] [ %s ] [ force_in ] auto_bridge_in" 1 ) +.endc + +*** SUBCIRCUIT DEFINITIONS +.include 74HCng_auto.lib +.param vcc=3 tripdt=6n + +aup force_in pullup +.model pullup d_pullup +adown force_out pulldown +.model pulldown d_pulldown + +.include ../adder_common.inc + +.END diff --git a/examples/digital/auto_bridge/shared_line.cir b/examples/digital/auto_bridge/shared_line.cir new file mode 100644 index 000000000..ce09890c2 --- /dev/null +++ b/examples/digital/auto_bridge/shared_line.cir @@ -0,0 +1,31 @@ +Test bidi_bridge direction changes and automatic bridging + +Va a 0 pulse 0 3 0 1u 1.2u 500u 1m +Vb b 0 pulse 0 3 0 1u 1.2u 100u 200u +Vctl ctl 0 pulse 0 3 10m 1u 1u 10m 20m + +Ainv ctl not_ctl invert +.model invert d_inverter + +* Transmitter/receiver for an analogue bus line + +.subckt driver in enable out bus +Atran in enable int tristate +Arec int out buffer +Rout int bus 20 // Make bus an analogue node, with bridge +.ends + +.model buffer d_buffer +.model tristate d_tristate + +Xa a ctl out_a bus driver +Xb b not_ctl out_b bus driver +Rload bus 0 1k + +.control +save a out_a b out_b +tran 1m 40m +plot out_a +listing e +.endc +.end