From a8619e17566019808ef53581c809317f7a0e49d4 Mon Sep 17 00:00:00 2001 From: Robert Larice Date: Mon, 17 Dec 2012 18:45:31 +0100 Subject: [PATCH] regression tests ... --- tests/Makefile.am | 4 +- tests/regression/Makefile.am | 5 ++ tests/regression/pwl-src/Makefile.am | 14 ++++ tests/regression/pwl-src/check-vsrc.sp | 99 +++++++++++++++++++++++++ tests/regression/pwl-src/isrc-pwl-1.cir | 79 ++++++++++++++++++++ tests/regression/pwl-src/isrc-pwl-1.out | 51 +++++++++++++ tests/regression/pwl-src/spinit | 1 + tests/regression/pwl-src/vsrc-pwl-1.cir | 85 +++++++++++++++++++++ tests/regression/pwl-src/vsrc-pwl-1.out | 67 +++++++++++++++++ tests/regression/pwl-src/vsrc-pwl-2.cir | 54 ++++++++++++++ tests/regression/pwl-src/vsrc-pwl-2.out | 46 ++++++++++++ 11 files changed, 504 insertions(+), 1 deletion(-) create mode 100644 tests/regression/Makefile.am create mode 100644 tests/regression/pwl-src/Makefile.am create mode 100644 tests/regression/pwl-src/check-vsrc.sp create mode 100644 tests/regression/pwl-src/isrc-pwl-1.cir create mode 100644 tests/regression/pwl-src/isrc-pwl-1.out create mode 100644 tests/regression/pwl-src/spinit create mode 100644 tests/regression/pwl-src/vsrc-pwl-1.cir create mode 100644 tests/regression/pwl-src/vsrc-pwl-1.out create mode 100644 tests/regression/pwl-src/vsrc-pwl-2.cir create mode 100644 tests/regression/pwl-src/vsrc-pwl-2.out diff --git a/tests/Makefile.am b/tests/Makefile.am index 543ccaf05..8b8963045 100644 --- a/tests/Makefile.am +++ b/tests/Makefile.am @@ -5,7 +5,8 @@ SUBDIRS = \ bsim4 \ bsimsoi \ hisim \ - hisimhv1 + hisimhv1 \ + regression if XSPICE_WANTED SUBDIRS += xspice @@ -31,6 +32,7 @@ DIST_SUBDIRS = \ mesa \ mos6 \ polezero \ + regression \ resistance \ sensitivity \ transient \ diff --git a/tests/regression/Makefile.am b/tests/regression/Makefile.am new file mode 100644 index 000000000..cef0d96af --- /dev/null +++ b/tests/regression/Makefile.am @@ -0,0 +1,5 @@ +## Process this file with automake to produce Makefile.in + +SUBDIRS = pwl-src + +MAINTAINERCLEANFILES = Makefile.in diff --git a/tests/regression/pwl-src/Makefile.am b/tests/regression/pwl-src/Makefile.am new file mode 100644 index 000000000..a6022fcd3 --- /dev/null +++ b/tests/regression/pwl-src/Makefile.am @@ -0,0 +1,14 @@ +## Process this file with automake to produce Makefile.in + +TESTS = \ + vsrc-pwl-1.cir \ + vsrc-pwl-2.cir \ + isrc-pwl-1.cir + +TESTS_ENVIRONMENT = SPICE_SCRIPTS=$(srcdir) $(SHELL) $(top_srcdir)/tests/bin/check.sh "$(top_builddir)/src/ngspice -r foobaz" + +EXTRA_DIST = \ + $(TESTS) \ + $(TESTS:.cir=.out) + +MAINTAINERCLEANFILES = Makefile.in diff --git a/tests/regression/pwl-src/check-vsrc.sp b/tests/regression/pwl-src/check-vsrc.sp new file mode 100644 index 000000000..257eeb910 --- /dev/null +++ b/tests/regression/pwl-src/check-vsrc.sp @@ -0,0 +1,99 @@ +check-vsrc + +.control + +begin + +if $argc ne 4 + echo "Error: usage: vv seq td ..pass vectors vv seq and time, and td" + goto bottom +end + +set vv = $argv[1] +set seq = $argv[2] +set td = $argv[3] + +echo "checking $vv" + +set expected_hits = $argv[4] + +let vv_length = length( time ) +let seq_length = length( $seq ) + +define match(x,gold,relerr) abs(x-gold) <= abs(relerr*gold) + + +*-------------------- +* compare golden seq with actual voltage + +let m = 0 +let k = 0 + +while k < vv_length + + let tmp_t = time [k] + let tmp_v = $vv [k] + + while tmp_t >= $seq [m+2] + $td + let m = m + 2 + end + + let t0 = $seq [m+0] + $td + let v0 = $seq [m+1] + let t1 = $seq [m+2] + $td + let v1 = $seq [m+3] + + if tmp_t <= t0 + let vgold = v0 + else + let vgold = v0 + ((v1 - v0)/(t1 - t0)) * (tmp_t - t0) + end + + if not match(tmp_v, vgold, 1.0e-9) + echo "ERROR: v[ $&k ] @ $&tmp_t is $&tmp_v expected $&vgold" + end + + let k = k + 1 +end + + +*-------------------- +* now search for the breakpoint hits + +let m = 0 +let k = 0 +let hit = 0 + +while k < vv_length and m < seq_length + + let tmp_t = time [k] + let tmp_s = $seq [m] + $td; + + if match(tmp_t, tmp_s, 1e-9) + let hit = hit + 1 + echo "INFO: hit at $&tmp_s" + end + + if tmp_t <= tmp_s + let k = k + 1 + else + let m = m + 2 + end + +end + +if hit ne $expected_hits + echo "error: breakpoint hits mismatch, actual $&hit, expected $expected_hits" +else + echo "info: breakpoint seem to be ok" +end + +echo "" + +label bottom + +* Local Variables: +* mode: spice +* End: + +end diff --git a/tests/regression/pwl-src/isrc-pwl-1.cir b/tests/regression/pwl-src/isrc-pwl-1.cir new file mode 100644 index 000000000..58c63be09 --- /dev/null +++ b/tests/regression/pwl-src/isrc-pwl-1.cir @@ -0,0 +1,79 @@ +isrc-pwl-1 + +* (compile (concat "../../../../w32/src/ngspice -b " buffer-file-name) t) +* (compile (concat "valgrind --track-origins=yes --leak-check=full --show-reachable=yes ../../../../w32/src/ngspice -b " buffer-file-name) t) +* +* broken, stept nicht wo er soll +* wenn r=0 td=15 ... +* in vsrcacct war td nicht berücksichtigt +* +* was ist die semantic von r genau, laut doku muss das exact matchen zu einem punkt +* +* case VSRC_TD: +* here->VSRCrdelay = value->rValue; +* break; +* case VSRC_R: { +* double end_time; +* here->VSRCr = value->rValue; +* here->VSRCrGiven = TRUE; +* +* here->VSRCrBreakpt = i; der index des matchenden elements ... +* if kleiner erster punkt dann erster punkt +* +* repeat_time = 0, ... +* repeat_time = (end_time - breakpt_time)* ++num_repeat; +* also der rest von punkten wird wiederhohlt +* wie genau ?? der punkt wird exact über den endpunkt gesetzt, step !! ? + +* FIXME, +* teste varianten mit step in zero time, auch an repeat grenze ... + +* manual example ? +* v2 1 0 pwl(0 -7 10ns -7 11ns -3 17ns -3 18ns -7 50ns -7) r=0 td=15ns + +i1 1 0 dc=0 pwl(0 10.0 10ns 10.0 11ns 11.0 17ns 11.0 18ns 18.0 1us 18.0) +i2 2 0 dc=0 pwl(0 10.0 10ns 10.0 11ns 11.0 17ns 11.0 18ns 18.0 1us 18.0) r=0 td=15ns +i3 3 0 dc=0 pwl(0 10.0 10ns 10.0 11ns 11.0 17ns 11.0 30ns 10.0) r=10ns + +r1 1 0 1 +r2 2 0 1 +r3 3 0 1 + +.control + +tran 200ps 100ns + +*-------------------- +* setup the tests +* wegen eines bugs, müssen die check-vsrc am schluss kommen (bug-2) +* FIXME, how to append vectoren ? + +let vv1 = -v(1) +let seq1 = @i1[pwl] +let td1 = 0 + + +let vv2 = -v(2) +let seq2 = @i2[pwl] +let td2 = 15ns + + +let vv3 = -v(3) +let td3 = 0 + +compose seq3 values ++ 0 10.0 10ns 10.0 11ns 11.0 17ns 11.0 30ns 10.0 ++ 31ns 11.0 37ns 11.0 50ns 10.0 ++ 51ns 11.0 57ns 11.0 70ns 10.0 ++ 71ns 11.0 77ns 11.0 90ns 10.0 ++ 91ns 11.0 97ns 11.0 110ns 10.0 ++ 111ns 11.0 117ns 11.0 130ns 10.0 + + +check-vsrc.sp vv1 seq1 td1 5 +check-vsrc.sp vv2 seq2 td2 5 +check-vsrc.sp vv3 seq3 td3 16 + +.endc + +.end diff --git a/tests/regression/pwl-src/isrc-pwl-1.out b/tests/regression/pwl-src/isrc-pwl-1.out new file mode 100644 index 000000000..268d93717 --- /dev/null +++ b/tests/regression/pwl-src/isrc-pwl-1.out @@ -0,0 +1,51 @@ +Circuit: isrc-pwl-1 + +Doing analysis at TEMP = 27.000000 and TNOM = 27.000000 + + +No. of Data Rows : 571 + +Circuit: check-vsrc + +checking vv1 +info: hit at 0 +info: hit at 1E-08 +info: hit at 1.1E-08 +info: hit at 1.7E-08 +info: hit at 1.8E-08 +info: breakpoint seem to be ok + + +Circuit: check-vsrc + +checking vv2 +info: hit at 1.5E-08 +info: hit at 2.5E-08 +info: hit at 2.6E-08 +info: hit at 3.2E-08 +info: hit at 3.3E-08 +info: breakpoint seem to be ok + + +Circuit: check-vsrc + +checking vv3 +info: hit at 0 +info: hit at 1E-08 +info: hit at 1.1E-08 +info: hit at 1.7E-08 +info: hit at 3E-08 +info: hit at 3.1E-08 +info: hit at 3.7E-08 +info: hit at 5E-08 +info: hit at 5.1E-08 +info: hit at 5.7E-08 +info: hit at 7E-08 +info: hit at 7.1E-08 +info: hit at 7.7E-08 +info: hit at 9E-08 +info: hit at 9.1E-08 +info: hit at 9.7E-08 +info: breakpoint seem to be ok + +Doing analysis at TEMP = 27.000000 and TNOM = 27.000000 diff --git a/tests/regression/pwl-src/spinit b/tests/regression/pwl-src/spinit new file mode 100644 index 000000000..677434fd7 --- /dev/null +++ b/tests/regression/pwl-src/spinit @@ -0,0 +1 @@ +set noacct diff --git a/tests/regression/pwl-src/vsrc-pwl-1.cir b/tests/regression/pwl-src/vsrc-pwl-1.cir new file mode 100644 index 000000000..0bf244b90 --- /dev/null +++ b/tests/regression/pwl-src/vsrc-pwl-1.cir @@ -0,0 +1,85 @@ +vsrc-pwl-1 + +* (compile (concat "../../../../w32/src/ngspice -b " buffer-file-name) t) +* (compile (concat "valgrind --track-origins=yes --leak-check=full --show-reachable=yes ../../../../w32/src/ngspice -b " buffer-file-name) t) +* +* broken, stept nicht wo er soll +* wenn r=0 td=15 ... +* in vsrcacct war td nicht berücksichtigt +* +* was ist die semantic von r genau, laut doku muss das exact matchen zu einem punkt +* +* case VSRC_TD: +* here->VSRCrdelay = value->rValue; +* break; +* case VSRC_R: { +* double end_time; +* here->VSRCr = value->rValue; +* here->VSRCrGiven = TRUE; +* +* here->VSRCrBreakpt = i; der index des matchenden elements ... +* if kleiner erster punkt dann erster punkt +* +* repeat_time = 0, ... +* repeat_time = (end_time - breakpt_time)* ++num_repeat; +* also der rest von punkten wird wiederhohlt +* wie genau ?? der punkt wird exact über den endpunkt gesetzt, step !! ? + +* FIXME, +* teste varianten mit step in zero time, auch an repeat grenze ... + +* manual example ? +* v2 1 0 pwl(0 -7 10ns -7 11ns -3 17ns -3 18ns -7 50ns -7) r=0 td=15ns + +v1 1 0 dc=0 pwl(0 10.0 10ns 10.0 11ns 11.0 17ns 11.0 18ns 18.0 1us 18.0) +v2 2 0 dc=0 pwl(0 10.0 10ns 10.0 11ns 11.0 17ns 11.0 18ns 18.0 1us 18.0) r=0 td=15ns +v3 3 0 dc=0 pwl(0 10.0 10ns 10.0 11ns 11.0 17ns 11.0 30ns 10.0) r=10ns +v4 4 0 dc=0 pwl(0 10.0 10ns 10.0 11ns 11.0 17ns 11.0 18ns 18.0 60ns 18.0) r=0 td=15ns + +.control + +tran 200ps 100ns + +*-------------------- +* setup the tests +* wegen eines bugs, müssen die check-vsrc am schluss kommen (bug-2) +* FIXME, how to append vectoren ? + +let vv1 = v(1) +let seq1 = @v1[pwl] +let td1 = 0 + + +let vv2 = v(2) +let seq2 = @v2[pwl] +let td2 = 15ns + + +let vv3 = v(3) +let td3 = 0 + +compose seq3 values ++ 0 10.0 10ns 10.0 11ns 11.0 17ns 11.0 30ns 10.0 ++ 31ns 11.0 37ns 11.0 50ns 10.0 ++ 51ns 11.0 57ns 11.0 70ns 10.0 ++ 71ns 11.0 77ns 11.0 90ns 10.0 ++ 91ns 11.0 97ns 11.0 110ns 10.0 ++ 111ns 11.0 117ns 11.0 130ns 10.0 + + +let vv4 = v(4) +let td4 = 15ns + +compose seq4 values ++ 0ns 10.0 10ns 10.0 11ns 11.0 17ns 11.0 18ns 18 60ns 18.0 ++ 60ns 10.0 70ns 10.0 71ns 11.0 77ns 11.0 78ns 18 120ns 18.0 + + +check-vsrc.sp vv1 seq1 td1 5 +check-vsrc.sp vv2 seq2 td2 5 +check-vsrc.sp vv3 seq3 td3 16 +check-vsrc.sp vv4 seq4 td4 10 + +.endc + +.end diff --git a/tests/regression/pwl-src/vsrc-pwl-1.out b/tests/regression/pwl-src/vsrc-pwl-1.out new file mode 100644 index 000000000..62ab860b0 --- /dev/null +++ b/tests/regression/pwl-src/vsrc-pwl-1.out @@ -0,0 +1,67 @@ +Circuit: vsrc-pwl-1 + +Doing analysis at TEMP = 27.000000 and TNOM = 27.000000 + + +No. of Data Rows : 586 + +Circuit: check-vsrc + +checking vv1 +info: hit at 0 +info: hit at 1E-08 +info: hit at 1.1E-08 +info: hit at 1.7E-08 +info: hit at 1.8E-08 +info: breakpoint seem to be ok + + +Circuit: check-vsrc + +checking vv2 +info: hit at 1.5E-08 +info: hit at 2.5E-08 +info: hit at 2.6E-08 +info: hit at 3.2E-08 +info: hit at 3.3E-08 +info: breakpoint seem to be ok + + +Circuit: check-vsrc + +checking vv3 +info: hit at 0 +info: hit at 1E-08 +info: hit at 1.1E-08 +info: hit at 1.7E-08 +info: hit at 3E-08 +info: hit at 3.1E-08 +info: hit at 3.7E-08 +info: hit at 5E-08 +info: hit at 5.1E-08 +info: hit at 5.7E-08 +info: hit at 7E-08 +info: hit at 7.1E-08 +info: hit at 7.7E-08 +info: hit at 9E-08 +info: hit at 9.1E-08 +info: hit at 9.7E-08 +info: breakpoint seem to be ok + + +Circuit: check-vsrc + +checking vv4 +info: hit at 1.5E-08 +info: hit at 2.5E-08 +info: hit at 2.6E-08 +info: hit at 3.2E-08 +info: hit at 3.3E-08 +info: hit at 7.5E-08 +info: hit at 8.5E-08 +info: hit at 8.6E-08 +info: hit at 9.2E-08 +info: hit at 9.3E-08 +info: breakpoint seem to be ok + +Doing analysis at TEMP = 27.000000 and TNOM = 27.000000 diff --git a/tests/regression/pwl-src/vsrc-pwl-2.cir b/tests/regression/pwl-src/vsrc-pwl-2.cir new file mode 100644 index 000000000..fef9d132a --- /dev/null +++ b/tests/regression/pwl-src/vsrc-pwl-2.cir @@ -0,0 +1,54 @@ +vsrc-pwl-2 + +* (compile (concat "../../../../w32/src/ngspice -b " buffer-file-name) t) +* (compile (concat "valgrind --track-origins=yes --leak-check=full --show-reachable=yes ../../../../w32/src/ngspice -b " buffer-file-name) t) +* +* emhasize `step' response +* geht im prinzip, aber es gibt nicht automatisch sampels +* kurz vor der jeweiligen discontinuity +* print.. zeigt die richtigen werte, +* aber plot linearinterpoliert schaut nicht so aus wie man es gerne hätte + +v1 1 0 dc=0 pwl(0 10.0 11ns 10.0 11ns 11.0 18ns 11.0 18ns 18.0 1us 18.0) +v2 2 0 dc=0 pwl(0 10.0 11ns 10.0 11ns 11.0 18ns 11.0 18ns 18.0 1us 18.0) r=0 td=15ns +v3 3 0 dc=0 pwl(0 10.0 11ns 10.0 11ns 11.0 18ns 11.0 18ns 10.0 31ns 10.0 31ns 11.0) r=11ns + +.control + +tran 200ps 100ns +reset +tran 200ps 100ns + +**-------------------- +** setup the tests +** wegen eines bugs, müssen die check-vsrc am schluss kommen (bug-2) +** FIXME, how to append vectoren ? +* +let vv1 = v(1) +let seq1 = @v1[pwl] +let td1 = 0 +* +* +let vv2 = v(2) +let seq2 = @v2[pwl] +let td2 = 15ns +* +* +let vv3 = v(3) +let td3 = 0 + +compose seq3 values ++ 0 10.0 11ns 10.0 11ns 11.0 18ns 11.0 18ns 10.0 31ns 10.0 ++ 31ns 11.0 38ns 11.0 38ns 10.0 51ns 10.0 ++ 51ns 11.0 58ns 11.0 58ns 10.0 71ns 10.0 ++ 71ns 11.0 78ns 11.0 78ns 10.0 91ns 10.0 ++ 91ns 11.0 98ns 11.0 98ns 10.0 111ns 10.0 ++ 111ns 11.0 118ns 11.0 118ns 10.0 131ns 10.0 + +check-vsrc.sp vv1 seq1 td1 3 +check-vsrc.sp vv2 seq2 td2 3 +check-vsrc.sp vv3 seq3 td3 11 + +.endc + +.end diff --git a/tests/regression/pwl-src/vsrc-pwl-2.out b/tests/regression/pwl-src/vsrc-pwl-2.out new file mode 100644 index 000000000..e47370671 --- /dev/null +++ b/tests/regression/pwl-src/vsrc-pwl-2.out @@ -0,0 +1,46 @@ +Circuit: vsrc-pwl-2 + +Doing analysis at TEMP = 27.000000 and TNOM = 27.000000 + + +No. of Data Rows : 547 +Doing analysis at TEMP = 27.000000 and TNOM = 27.000000 + + +No. of Data Rows : 547 + +Circuit: check-vsrc + +checking vv1 +info: hit at 0 +info: hit at 1.1E-08 +info: hit at 1.8E-08 +info: breakpoint seem to be ok + + +Circuit: check-vsrc + +checking vv2 +info: hit at 1.5E-08 +info: hit at 2.6E-08 +info: hit at 3.3E-08 +info: breakpoint seem to be ok + + +Circuit: check-vsrc + +checking vv3 +info: hit at 0 +info: hit at 1.1E-08 +info: hit at 1.8E-08 +info: hit at 3.1E-08 +info: hit at 3.8E-08 +info: hit at 5.1E-08 +info: hit at 5.8E-08 +info: hit at 7.1E-08 +info: hit at 7.8E-08 +info: hit at 9.1E-08 +info: hit at 9.8E-08 +info: breakpoint seem to be ok + +Doing analysis at TEMP = 27.000000 and TNOM = 27.000000