From 882acb73fddd5d3b5646801eee734e83c4fb15a9 Mon Sep 17 00:00:00 2001 From: Holger Vogt Date: Sun, 8 Jun 2025 10:09:28 +0200 Subject: [PATCH] Add a monitoring output the the seegen instance --- examples/xspice/see/CMOSOpAmp/CMOS-OP1.cir | 4 +-- examples/xspice/see/CMOSOpAmp/cmos_sub.mod | 4 +-- examples/xspice/see/CMOSOpAmp/seegen4.mod | 4 +-- .../xspice/see/ihp_simple_sram_seegen.net | 2 +- .../see/ihp_simple_sram_seegen_ctrl.net | 2 +- .../see/ihp_simple_sram_seegen_subckt.net | 4 +-- .../ihp_simple_sram_seegen_subckt_vary.net | 4 +-- examples/xspice/see/repeat_loop_seegen.net | 4 +-- examples/xspice/see/seegen_cm1.cir | 2 +- src/xspice/icm/xtradev/seegenerator/cfunc.mod | 6 +++-- .../icm/xtradev/seegenerator/ifspec.ifs | 26 ++++++++++++++----- 11 files changed, 38 insertions(+), 24 deletions(-) diff --git a/examples/xspice/see/CMOSOpAmp/CMOS-OP1.cir b/examples/xspice/see/CMOSOpAmp/CMOS-OP1.cir index 2e2b2e480..ba2f849a0 100644 --- a/examples/xspice/see/CMOSOpAmp/CMOS-OP1.cir +++ b/examples/xspice/see/CMOSOpAmp/CMOS-OP1.cir @@ -7,7 +7,7 @@ XMN9 Vbias Vbias 0 0 NCH W=5u L=1.4u V5 in+ 0 DC 1.65 R1 out in- 100k R2 in in- 20k -V4 in 0 DC 1.65 SIN( 1.65 100m 1k 0 0 0 ) AC 1 +V4 in 0 DC 1.65 SIN( 1.65 100m 20k 0 0 0 ) AC 1 XMN3 out Vbias 0 0 NCH W=17.4u L=1.4u C2 out 0 2p XMP2 out VGP2 Vcc Vcc PCH W=14.5u L=1.4u @@ -23,7 +23,7 @@ XMP8 VGP2 VGP4P8 Vcc Vcc PCH W=2.8u L=1.4u set xbrushwidth=2 tran 20n 2m -plot v(VGP4P8) +plot v(VGP4P8) v(xu1.mon)*5000+3 plot in out ac dec 10 1 1Meg diff --git a/examples/xspice/see/CMOSOpAmp/cmos_sub.mod b/examples/xspice/see/CMOSOpAmp/cmos_sub.mod index c72096db9..a38707089 100644 --- a/examples/xspice/see/CMOSOpAmp/cmos_sub.mod +++ b/examples/xspice/see/CMOSOpAmp/cmos_sub.mod @@ -4,10 +4,10 @@ .include modelcard.pmos .subckt NCH D G S B W=1 L=1 -MN1 D G S B N1 W={W} L={L} AS={3*L*W} AD={3*L*W} PS={6*L+W} AS={6*L+W} +MN1 D G S B N1 W={W} L={L} AS={3*L*W} AD={3*L*W} PS={6*L+W} PD={6*L+W} .ends .subckt PCH D G S B W=1 L=1 -MP1 D G S B P1 W={W} L={L} AS={3*L*W} AD={3*L*W} PS={6*L+W} AS={6*L+W} +MP1 D G S B P1 W={W} L={L} AS={3*L*W} AD={3*L*W} PS={6*L+W} PD={6*L+W} .ends diff --git a/examples/xspice/see/CMOSOpAmp/seegen4.mod b/examples/xspice/see/CMOSOpAmp/seegen4.mod index c29d787fe..55969ce88 100644 --- a/examples/xspice/see/CMOSOpAmp/seegen4.mod +++ b/examples/xspice/see/CMOSOpAmp/seegen4.mod @@ -5,6 +5,6 @@ .param Inull = 'tochar/(tfall-trise)' * Eponential current source without control input * only NMOS nodes with reference GND (substrate). -aseegen1 NULL [%i(n1) %i(n2) %i(n3) %i(n4)] seemod1 -.model seemod1 seegen (tdelay = 0.62m tperiod=0.1m inull='Inull' perlim=FALSE) +aseegen1 NULL mon [%i(n1) %i(n2) %i(n3) %i(n4)] seemod1 +.model seemod1 seegen (tdelay = 0.62m tperiod=0.01m inull='Inull' perlim=FALSE) .ends \ No newline at end of file diff --git a/examples/xspice/see/ihp_simple_sram_seegen.net b/examples/xspice/see/ihp_simple_sram_seegen.net index 26d7e5a33..d6e8900ff 100644 --- a/examples/xspice/see/ihp_simple_sram_seegen.net +++ b/examples/xspice/see/ihp_simple_sram_seegen.net @@ -21,7 +21,7 @@ Vbln bln 0 0 *V1 in gnd pulse(0 'vdd' 0p 200p 100p 5n 10n) * Eponential current source without control input -aseegen1 NULL [%id(n1 m1) %id(n2 m2) %id(n1 m1) %id(n2 m2)] seemod1 +aseegen1 NULL mon [%id(n1 m1) %id(n2 m2) %id(n1 m1) %id(n2 m2)] seemod1 .model seemod1 seegen (tdelay = 11n tperiod=25n inull='Inull') Xnot1 n1 vdd vss n2 not1 diff --git a/examples/xspice/see/ihp_simple_sram_seegen_ctrl.net b/examples/xspice/see/ihp_simple_sram_seegen_ctrl.net index ce13a7dca..e7f5b6ca7 100644 --- a/examples/xspice/see/ihp_simple_sram_seegen_ctrl.net +++ b/examples/xspice/see/ihp_simple_sram_seegen_ctrl.net @@ -19,7 +19,7 @@ Vbln bln 0 0 Vctrl ctrl 0 pulse (0 1 10n 1n 1n 1 1) * Exponential current source with control input -aseegen1 ctrl [%id(n1 m1) %id(n2 m2) %id(n1 m1) %id(n2 m2)] seemod1 +aseegen1 ctrl mon [%id(n1 m1) %id(n2 m2) %id(n1 m1) %id(n2 m2)] seemod1 .model seemod1 seegen (tdelay = 8n tperiod=25n) Xnot1 n1 vdd vss n2 not1 diff --git a/examples/xspice/see/ihp_simple_sram_seegen_subckt.net b/examples/xspice/see/ihp_simple_sram_seegen_subckt.net index 7b689f852..f927e4344 100644 --- a/examples/xspice/see/ihp_simple_sram_seegen_subckt.net +++ b/examples/xspice/see/ihp_simple_sram_seegen_subckt.net @@ -19,10 +19,10 @@ Vbl1 bl1 0 'vdd' Vbl2 bl2 0 0 **** SEE generator without control input, double exponential current sources -aseegen1 NULL [%id(xcell.n1 m1) %id(xcell.n2 m2) %id(xcell.n1 m1) %id(xcell.n2 m2)] seemod1 +aseegen1 NULL mon [%id(xcell.n1 m1) %id(xcell.n2 m2) %id(xcell.n1 m1) %id(xcell.n2 m2)] seemod1 .model seemod1 seegen (tdelay = 11n tperiod=25n let='let' cdepth='cdepth' tfall='tfall' trise='trise') * alternative syntax, if no current measurement required and reference nodes are GND -*aseegen1 NULL [%i(xcell.n1) %i(xcell.n2) %i(xcell.n1) %i(xcell.n2)] seemod1 +*aseegen1 NULL mon [%i(xcell.n1) %i(xcell.n2) %i(xcell.n1) %i(xcell.n2)] seemod1 **** the SRAM cell Xcell bl1 bl2 wl vdd vss srcell diff --git a/examples/xspice/see/ihp_simple_sram_seegen_subckt_vary.net b/examples/xspice/see/ihp_simple_sram_seegen_subckt_vary.net index 5bd6c80da..30b57790d 100644 --- a/examples/xspice/see/ihp_simple_sram_seegen_subckt_vary.net +++ b/examples/xspice/see/ihp_simple_sram_seegen_subckt_vary.net @@ -23,10 +23,10 @@ Vbl1 bl1 0 'vdd' Vbl2 bl2 0 0 **** SEE generator without control input, double exponential current sources -aseegen1 NULL [%id(xcell.n1 m1) %id(xcell.n2 m2) %id(xcell.n1 m1) %id(xcell.n2 m2)] seemod1 +aseegen1 NULL mon [%id(xcell.n1 m1) %id(xcell.n2 m2) %id(xcell.n1 m1) %id(xcell.n2 m2)] seemod1 .model seemod1 seegen (tdelay = 11n tperiod=25n tfall='tfall' trise='trise' let='let' cdepth='d') * alternative syntax, if no current measurement required and reference nodes are GND -*aseegen1 NULL [%i(xcell.n1) %i(xcell.n2) %i(xcell.n1) %i(xcell.n2)] seemod1 +*aseegen1 NULL mon [%i(xcell.n1) %i(xcell.n2) %i(xcell.n1) %i(xcell.n2)] seemod1 **** the SRAM cell Xcell bl1 bl2 wl vdd vss srcell diff --git a/examples/xspice/see/repeat_loop_seegen.net b/examples/xspice/see/repeat_loop_seegen.net index 222814719..9f212ff07 100644 --- a/examples/xspice/see/repeat_loop_seegen.net +++ b/examples/xspice/see/repeat_loop_seegen.net @@ -11,10 +11,10 @@ R4 n4 0 1e4 **** SEE generator without control input, double exponential current sources -aseegen1 NULL [%id(n1 0) %id(n2 0) %id(n3 0) %id(n4 0)] seemod1 +aseegen1 NULL mon [%id(n1 0) %id(n2 0) %id(n3 0) %id(n4 0)] seemod1 .model seemod1 seegen (tdelay = 11n tperiod=25n let='let' cdepth='cdepth' trise='trise' tfall='tfall') * alternative syntax, if no current measurement required and reference nodes are GND -*aseegen1 NULL [%i(n1) %i(n2) %i(n3) %i(n4)] seemod1 +*aseegen1 NULL mon [%i(n1) %i(n2) %i(n3) %i(n4)] seemod1 diff --git a/examples/xspice/see/seegen_cm1.cir b/examples/xspice/see/seegen_cm1.cir index a4bd7e371..8d4915e78 100644 --- a/examples/xspice/see/seegen_cm1.cir +++ b/examples/xspice/see/seegen_cm1.cir @@ -1,6 +1,6 @@ Test of seegen code model -aseegen1 NULL [%id(n1 p1) %id(n2 p2) %id(n3 p3)] seemod1 +aseegen1 NULL mon [%id(n1 p1) %id(n2 p2) %id(n3 p3)] seemod1 .model seemod1 seegen (tdelay = 5n tperiod=4.5n) Rsee1 n1 0 1 diff --git a/src/xspice/icm/xtradev/seegenerator/cfunc.mod b/src/xspice/icm/xtradev/seegenerator/cfunc.mod index 11bee5c74..5f21e626b 100644 --- a/src/xspice/icm/xtradev/seegenerator/cfunc.mod +++ b/src/xspice/icm/xtradev/seegenerator/cfunc.mod @@ -222,8 +222,10 @@ void cm_seegen(ARGS) /* structure holding parms, *last_t_value = 1e12; /* stop any output */ } } - if (*pulse_number - 1 < PORT_SIZE(out)) - OUTPUT(out[*pulse_number - 1]) = out; + if (*pulse_number - 1 < PORT_SIZE(out)) { + OUTPUT(out[*pulse_number - 1]) = out; + OUTPUT(mon) = out; + } } } diff --git a/src/xspice/icm/xtradev/seegenerator/ifspec.ifs b/src/xspice/icm/xtradev/seegenerator/ifspec.ifs index 58d28f039..cee53b78f 100644 --- a/src/xspice/icm/xtradev/seegenerator/ifspec.ifs +++ b/src/xspice/icm/xtradev/seegenerator/ifspec.ifs @@ -29,14 +29,26 @@ Description: "single event effect generator" PORT_TABLE: -Port_Name: ctrl out -Description: "control input" "output" +Port_Name: ctrl mon +Description: "control input" "monitor" Direction: in out -Default_Type: v i -Allowed_Types: [v,vd,i,id] [i,id] -Vector: no yes -Vector_Bounds: - [1 -] -Null_Allowed: yes no +Default_Type: v v +Allowed_Types: [v,vd,i,id] [v] +Vector: no no +Vector_Bounds: - - +Null_Allowed: yes yes + + +PORT_TABLE: + +Port_Name: out +Description: "output" +Direction: out +Default_Type: i +Allowed_Types: [i,id] +Vector: yes +Vector_Bounds: [1 -] +Null_Allowed: no PARAMETER_TABLE: