diff --git a/src/spicelib/devices/isrc/isrcacct.c b/src/spicelib/devices/isrc/isrcacct.c
index b71987f30..abf232f01 100644
--- a/src/spicelib/devices/isrc/isrcacct.c
+++ b/src/spicelib/devices/isrc/isrcacct.c
@@ -62,16 +62,21 @@ ISRCaccept(CKTcircuit *ckt, GENmodel *inModel)
                         TD = here->ISRCfunctionOrder > 2
                             ? here->ISRCcoeffs[2] : 0.0;
                         TR = here->ISRCfunctionOrder > 3
-                            && here->ISRCcoeffs[3] != 0.0
+                            && here->ISRCcoeffs[3] > 0.0
                             ? here->ISRCcoeffs[3] : ckt->CKTstep;
                         TF = here->ISRCfunctionOrder > 4
-                            && here->ISRCcoeffs[4] != 0.0
+                            && here->ISRCcoeffs[4] > 0.0
                             ? here->ISRCcoeffs[4] : ckt->CKTstep;
-                        PW = here->ISRCfunctionOrder > 5
-                            && here->ISRCcoeffs[5] != 0.0
-                            ? here->ISRCcoeffs[5] : ckt->CKTfinalTime;
+                        if (here->ISRCfunctionOrder == 5) {
+                            PW = 0.0;
+                        }
+                        else {
+                            PW = here->ISRCfunctionOrder > 5
+                                && here->ISRCcoeffs[5] >= 0.0
+                                ? here->ISRCcoeffs[5] : ckt->CKTfinalTime;
+                        }
                         PER = here->ISRCfunctionOrder > 6
-                            && here->ISRCcoeffs[6] != 0.0
+                            && here->ISRCcoeffs[6] > 0.0
                             ? here->ISRCcoeffs[6] : ckt->CKTfinalTime;
                         PHASE = here->ISRCfunctionOrder > 7
                             ? here->ISRCcoeffs[7] : 0.0;
diff --git a/src/spicelib/devices/isrc/isrcload.c b/src/spicelib/devices/isrc/isrcload.c
index 67e96e3bf..5e02b0372 100644
--- a/src/spicelib/devices/isrc/isrcload.c
+++ b/src/spicelib/devices/isrc/isrcload.c
@@ -81,19 +81,24 @@ ISRCload(GENmodel *inModel, CKTcircuit *ckt)
                         V1 = here->ISRCcoeffs[0];
                         V2 = here->ISRCcoeffs[1];
                         TD = here->ISRCfunctionOrder > 2
-                           ? here->ISRCcoeffs[2] : 0.0;
+                            ? here->ISRCcoeffs[2] : 0.0;
                         TR = here->ISRCfunctionOrder > 3
-                           && here->ISRCcoeffs[3] != 0.0
-                           ? here->ISRCcoeffs[3] : ckt->CKTstep;
+                            && here->ISRCcoeffs[3] > 0.0
+                            ? here->ISRCcoeffs[3] : ckt->CKTstep;
                         TF = here->ISRCfunctionOrder > 4
-                           && here->ISRCcoeffs[4] != 0.0
-                           ? here->ISRCcoeffs[4] : ckt->CKTstep;
-                        PW = here->ISRCfunctionOrder > 5
-                           && here->ISRCcoeffs[5] != 0.0
-                           ? here->ISRCcoeffs[5] : ckt->CKTfinalTime;
+                            && here->ISRCcoeffs[4] > 0.0
+                            ? here->ISRCcoeffs[4] : ckt->CKTstep;
+                        if (here->ISRCfunctionOrder == 5) {
+                            PW = 0.0;
+                        }
+                        else {
+                            PW = here->ISRCfunctionOrder > 5
+                                && here->ISRCcoeffs[5] >= 0.0
+                                ? here->ISRCcoeffs[5] : ckt->CKTfinalTime;
+                        }
                         PER = here->ISRCfunctionOrder > 6
-                           && here->ISRCcoeffs[6] != 0.0
-                           ? here->ISRCcoeffs[6] : ckt->CKTfinalTime;
+                            && here->ISRCcoeffs[6] > 0.0
+                            ? here->ISRCcoeffs[6] : ckt->CKTfinalTime;
 
                         /* shift time by delay time TD */
                         time -=  TD;
diff --git a/src/spicelib/devices/vsrc/vsrcacct.c b/src/spicelib/devices/vsrc/vsrcacct.c
index df890ed76..41ed6f63a 100644
--- a/src/spicelib/devices/vsrc/vsrcacct.c
+++ b/src/spicelib/devices/vsrc/vsrcacct.c
@@ -59,16 +59,21 @@ VSRCaccept(CKTcircuit *ckt, GENmodel *inModel)
                         TD = here->VSRCfunctionOrder > 2
                             ? here->VSRCcoeffs[2] : 0.0;
                         TR = here->VSRCfunctionOrder > 3
-                            && here->VSRCcoeffs[3] != 0.0
+                            && here->VSRCcoeffs[3] > 0.0
                             ? here->VSRCcoeffs[3] : ckt->CKTstep;
                         TF = here->VSRCfunctionOrder > 4
-                            && here->VSRCcoeffs[4] != 0.0
+                            && here->VSRCcoeffs[4] > 0.0
                             ? here->VSRCcoeffs[4] : ckt->CKTstep;
-                        PW = here->VSRCfunctionOrder > 5
-                            && here->VSRCcoeffs[5] != 0.0
-                            ? here->VSRCcoeffs[5] : ckt->CKTfinalTime;
+                        if (here->VSRCfunctionOrder == 5) {
+                            PW = 0.0;
+                        }
+                        else {
+                            PW = here->VSRCfunctionOrder > 5
+                                && here->VSRCcoeffs[5] >= 0.0
+                                ? here->VSRCcoeffs[5] : ckt->CKTfinalTime;
+                        }
                         PER = here->VSRCfunctionOrder > 6
-                            && here->VSRCcoeffs[6] != 0.0
+                            && here->VSRCcoeffs[6] > 0.0
                             ? here->VSRCcoeffs[6] : ckt->CKTfinalTime;
                         PHASE = here->VSRCfunctionOrder > 7
                             ? here->VSRCcoeffs[7] : 0.0;
diff --git a/src/spicelib/devices/vsrc/vsrcload.c b/src/spicelib/devices/vsrc/vsrcload.c
index 6da9b1a39..5bb468994 100644
--- a/src/spicelib/devices/vsrc/vsrcload.c
+++ b/src/spicelib/devices/vsrc/vsrcload.c
@@ -86,37 +86,49 @@ VSRCload(GENmodel *inModel, CKTcircuit *ckt)
                 } else {
                     time = ckt->CKTtime;
                 }
-                /* use the transient functions */
+                /* use the transient functions. */
                 switch(here->VSRCfunctionType) {
 
                     default:
                         value = here->VSRCdcValue;
                         break;
 
-                    case PULSE: {
-                        double V1, V2, TD, TR, TF, PW, PER;
-                        double basetime = 0;
-                        double PHASE;
-                        double phase;
-                        double deltat;
-                        double tmax = 1e99;
+                case PULSE: {
+                    /* Parameter limits :
+                      TR negative or 0 --> TR = ckt->CKTstep
+                      TF negative or 0 --> TF = ckt->CKTstep
+                      if PW not given, but TR and TF --> PW = 0
+                      PW < 0 --> PW = ckt->CKTfinalTime
+                      PER <= 0 --> PER = ckt->CKTfinalTime
+                    */
+                    double V1, V2, TD, TR, TF, PW, PER;
+                    double basetime = 0;
+                    double PHASE;
+                    double phase;
+                    double deltat;
+                    double tmax = 1e99;
 
-                        V1 = here->VSRCcoeffs[0];
-                        V2 = here->VSRCcoeffs[1];
-                        TD = here->VSRCfunctionOrder > 2
-                           ? here->VSRCcoeffs[2] : 0.0;
-                        TR = here->VSRCfunctionOrder > 3
-                           && here->VSRCcoeffs[3] != 0.0
-                           ? here->VSRCcoeffs[3] : ckt->CKTstep;
-                        TF = here->VSRCfunctionOrder > 4
-                           && here->VSRCcoeffs[4] != 0.0
-                           ? here->VSRCcoeffs[4] : ckt->CKTstep;
+                    V1 = here->VSRCcoeffs[0];
+                    V2 = here->VSRCcoeffs[1];
+                    TD = here->VSRCfunctionOrder > 2
+                        ? here->VSRCcoeffs[2] : 0.0;
+                    TR = here->VSRCfunctionOrder > 3
+                        && here->VSRCcoeffs[3] > 0.0
+                        ? here->VSRCcoeffs[3] : ckt->CKTstep;
+                    TF = here->VSRCfunctionOrder > 4
+                        && here->VSRCcoeffs[4] > 0.0
+                        ? here->VSRCcoeffs[4] : ckt->CKTstep;
+                    if (here->VSRCfunctionOrder == 5) {
+                        PW = 0.0;
+                    }
+                    else {
                         PW = here->VSRCfunctionOrder > 5
-                           && here->VSRCcoeffs[5] != 0.0
-                           ? here->VSRCcoeffs[5] : ckt->CKTfinalTime;
-                        PER = here->VSRCfunctionOrder > 6
-                           && here->VSRCcoeffs[6] != 0.0
-                           ? here->VSRCcoeffs[6] : ckt->CKTfinalTime;
+                            && here->VSRCcoeffs[5] >= 0.0
+                            ? here->VSRCcoeffs[5] : ckt->CKTfinalTime;
+                    }
+                    PER = here->VSRCfunctionOrder > 6
+                        && here->VSRCcoeffs[6] > 0.0
+                        ? here->VSRCcoeffs[6] : ckt->CKTfinalTime;
 
                         /* shift time by delay time TD */
                         time -=  TD;