diff --git a/examples/xspice/pll/README b/examples/xspice/pll/README new file mode 100644 index 000000000..c4bcbc9cd --- /dev/null +++ b/examples/xspice/pll/README @@ -0,0 +1,14 @@ +This directory contains a mixed mode pll, combining +ngspice and XSPICE circuit blocks. +The pll consists of the following blocks: +voltage controlled oscillator: vco_sub.cir +digital divider and frequency reference: pll-xspice.cir +phase frequency detector: f-p-det-d-sub.cir +loop filter: loop-filter.cir +main simulation control: pll-xspice.cir + +Two test files are included: +test-vco.cir simulates vco frequency versus control voltage +test-f-p-det.cir simulates the phase frequency detector and the loop filter. + +The main building blocks are organised as subcircuits. diff --git a/examples/xspice/pll/f-p-det-d-sub.cir b/examples/xspice/pll/f-p-det-d-sub.cir new file mode 100644 index 000000000..cdd5af9e9 --- /dev/null +++ b/examples/xspice/pll/f-p-det-d-sub.cir @@ -0,0 +1,16 @@ +* frequency-phase detector according to +* http://www.uwe-kerwien.de/pll/pll-phasenvergleich.htm + +.subckt f-p-det d_R d_V d_U d_U_ d_D d_D_ + +aa1 [d_U d_D] d_rset and1 +.model and1 d_and(rise_delay = 1e-10 fall_delay = 0.1e-9 ++ input_load = 0.5e-12) + +ad1 d_d1 d_R d_d0 d_rset d_U d_U_ flop1 +ad2 d_d1 d_V d_d0 d_rset d_D d_D_ flop1 +.model flop1 d_dff(clk_delay = 1.0e-10 set_delay = 1.0e-10 ++ reset_delay = 1.0e-10 ic = 2 rise_delay = 1.0e-10 ++ fall_delay = 1e-10) + +.ends f-p-det diff --git a/examples/xspice/pll/loop-filter.cir b/examples/xspice/pll/loop-filter.cir new file mode 100644 index 000000000..ac1ebc00f --- /dev/null +++ b/examples/xspice/pll/loop-filter.cir @@ -0,0 +1,31 @@ +* loop filter for pll +* in: d_up d_down digital data +* out: vout, vco control voltage +* according to http://www.uwe-kerwien.de/pll/pll-schleifenfilter.htm + +.subckt loopf d_U d_D vout + +.param loadcur=5m +.param initcond=2.5 + +v1 vtop 0 1 +v2 vbot 0 -1 + +abridge-f1 [d_U d_D] [u1 d1] dac1 +.model dac1 dac_bridge(out_low = 0 out_high = 1 out_undef = 0.5 ++ input_load = 5.0e-12 t_rise = 1e-10 ++ t_fall = 1e-10) + +*top switched current source +Gtop vtop vout cur='loadcur*v(u1)' +*bottom switched current source +Gbot vout vbot cur='loadcur*v(d1)' + +*passive filter elements +.ic v(vout)='initcond' v(c1)='initcond' +R2 vout c1 200 +C1 c1 0 5n +C2 vout 0 5n +Rshunt vout 0 10000k + +.ends diff --git a/examples/xspice/pll/pll-xspice.cir b/examples/xspice/pll/pll-xspice.cir new file mode 100644 index 000000000..c0bd85ca8 --- /dev/null +++ b/examples/xspice/pll/pll-xspice.cir @@ -0,0 +1,133 @@ +* pll circuit using xspice code models + +.param vcc=3.3 +.param divisor=40 +.param fref=10e6 +.csparam simtime=20u + +.global d_d0 d_d1 + +vdd dd 0 dc 'vcc' +*vco cont 0 dc 1.9 + +*PULSE(V1 V2 TD TR TF PW PER) +* 10 MHz reference frequency +* PULSE(V1 V2 TD TR TF PW PER) +vref ref 0 dc 0 pulse(0 'vcc' 10n 1n 1n '1/fref/2' '1/fref') +abridgeref [ref] [d_ref] adc_vbuf +.model adc_vbuf adc_bridge(in_low = 0.5 in_high = 0.5) + +*digital zero +vzero z 0 dc 0 +abridgev3 [z] [d_d0] adc_vbuf +.model adc_vbuf adc_bridge(in_low = 'vcc*0.5' in_high = 'vcc*0.5') +*digital one +ainv1 d_d0 d_d1 invd1 +.model invd1 d_inverter(rise_delay = 1e-10 fall_delay = 1e-10) + +* vco +.include vco_sub.cir +* buf: analog out +* d_digout: digital out +* cont: analog control voltage +* dd: analog supply voltage +xvco buf d_digout cont dd ro_vco + +* digital divider +adiv1 d_digout d_divout divider +.model divider d_fdiv(div_factor = 'divisor' high_cycles = 'divisor/2' ++ i_count = 4 rise_delay = 1e-10 ++ fall_delay = 1e-10) + +* frequency phase detector +.include f-p-det-d-sub.cir +Xfpdet d_divout d_ref d_U d_Un d_D d_Dn f-p-det + +* loop filter +.include loop-filter.cir +Xlf d_U d_D cont loopf + +* d to a for plotting +abridge-w1 [d_divout d_ref d_U d_D] [s1 s2 u1 d1] dac1 +.model dac1 dac_bridge(out_low = 0 out_high = 1 out_undef = 0.5 ++ input_load = 5.0e-12 t_rise = 1e-10 ++ t_fall = 1e-10) + +.control +set xtrtol=2 +tran 0.1n $&simtime uic +rusage +plot cont s1 s2+1.2 u1+2.4 d1+3.6 +plot cont +.endc + +*model = bsim3v3 +*Berkeley Spice Compatibility +* Lmin= .35 Lmax= 20 Wmin= .6 Wmax= 20 +.model N1 NMOS +*+version = 3.2.4 ++version = 3.3.0 ++Level= 8 ++Tnom=27.0 ++Nch= 2.498E+17 Tox=9E-09 Xj=1.00000E-07 ++Lint=9.36e-8 Wint=1.47e-7 ++Vth0= .6322 K1= .756 K2= -3.83e-2 K3= -2.612 ++Dvt0= 2.812 Dvt1= 0.462 Dvt2=-9.17e-2 ++Nlx= 3.52291E-08 W0= 1.163e-6 ++K3b= 2.233 ++Vsat= 86301.58 Ua= 6.47e-9 Ub= 4.23e-18 Uc=-4.706281E-11 ++Rdsw= 650 U0= 388.3203 wr=1 ++A0= .3496967 Ags=.1 B0=0.546 B1= 1 ++ Dwg = -6.0E-09 Dwb = -3.56E-09 Prwb = -.213 ++Keta=-3.605872E-02 A1= 2.778747E-02 A2= .9 ++Voff=-6.735529E-02 NFactor= 1.139926 Cit= 1.622527E-04 ++Cdsc=-2.147181E-05 ++Cdscb= 0 Dvt0w = 0 Dvt1w = 0 Dvt2w = 0 ++ Cdscd = 0 Prwg = 0 ++Eta0= 1.0281729E-02 Etab=-5.042203E-03 ++Dsub= .31871233 ++Pclm= 1.114846 Pdiblc1= 2.45357E-03 Pdiblc2= 6.406289E-03 ++Drout= .31871233 Pscbe1= 5000000 Pscbe2= 5E-09 Pdiblcb = -.234 ++Pvag= 0 delta=0.01 ++ Wl = 0 Ww = -1.420242E-09 Wwl = 0 ++ Wln = 0 Wwn = .2613948 Ll = 1.300902E-10 ++ Lw = 0 Lwl = 0 Lln = .316394 ++ Lwn = 0 ++kt1=-.3 kt2=-.051 ++At= 22400 ++Ute=-1.48 ++Ua1= 3.31E-10 Ub1= 2.61E-19 Uc1= -3.42e-10 ++Kt1l=0 Prt=764.3 + +.model P1 PMOS +*+version = 3.2.4 ++version = 3.3.0 ++Level= 8 ++Tnom=27.0 ++Nch= 3.533024E+17 Tox=9E-09 Xj=1.00000E-07 ++Lint=6.23e-8 Wint=1.22e-7 ++Vth0=-.6732829 K1= .8362093 K2=-8.606622E-02 K3= 1.82 ++Dvt0= 1.903801 Dvt1= .5333922 Dvt2=-.1862677 ++Nlx= 1.28e-8 W0= 2.1e-6 ++K3b= -0.24 Prwg=-0.001 Prwb=-0.323 ++Vsat= 103503.2 Ua= 1.39995E-09 Ub= 1.e-19 Uc=-2.73e-11 ++ Rdsw= 460 U0= 138.7609 ++A0= .4716551 Ags=0.12 ++Keta=-1.871516E-03 A1= .3417965 A2= 0.83 ++Voff=-.074182 NFactor= 1.54389 Cit=-1.015667E-03 ++Cdsc= 8.937517E-04 ++Cdscb= 1.45e-4 Cdscd=1.04e-4 ++ Dvt0w=0.232 Dvt1w=4.5e6 Dvt2w=-0.0023 ++Eta0= 6.024776E-02 Etab=-4.64593E-03 ++Dsub= .23222404 ++Pclm= .989 Pdiblc1= 2.07418E-02 Pdiblc2= 1.33813E-3 ++Drout= .3222404 Pscbe1= 118000 Pscbe2= 1E-09 ++Pvag= 0 ++kt1= -0.25 kt2= -0.032 prt=64.5 ++At= 33000 ++Ute= -1.5 ++Ua1= 4.312e-9 Ub1= 6.65e-19 Uc1= 0 ++Kt1l=0 + + +.end diff --git a/examples/xspice/pll/test-f-p-det.cir b/examples/xspice/pll/test-f-p-det.cir new file mode 100644 index 000000000..fe3d41d25 --- /dev/null +++ b/examples/xspice/pll/test-f-p-det.cir @@ -0,0 +1,40 @@ +* test frequency-phase detector similar to 12040 + +.param vcc=3.3 +.global d_d0 d_d1 + +*PULSE(V1 V2 TD TR TF PW PER) +v1 1 0 dc 0 pulse(0 'vcc' 10n 1n 1n 10n 20n) +v2 2 0 dc 0 pulse(0 'vcc' 8n 1n 1n 10n 20n) + +*digital zero +v3 3 0 dc 0 +abridgev1 [1 2 3] [d_sig1 d_sig2 d_d0] adc_vbuf +.model adc_vbuf adc_bridge(in_low = 'vcc*0.5' in_high = 'vcc*0.5') +*digital one +ainv1 d_d0 d_d1 invd1 +.model invd1 d_inverter(rise_delay = 1e-10 fall_delay = 1e-10) + +Xfpdet d_sig1 d_sig2 d_U d_Un d_D d_Dn f-p-det + +*.include f-p-det-sub.cir +.include f-p-det-d-sub.cir + +* d to a for plotting +abridge-w1 [d_sig1 d_sig2 d_U d_D] [s1 s2 u1 d1] dac1 +.model dac1 dac_bridge(out_low = 0 out_high = 1 out_undef = 0.5 ++ input_load = 5.0e-12 t_rise = 1e-10 ++ t_fall = 1e-10) + +* loop filter +.include loop-filter.cir +Xlf d_u d_D vco loopf + +.control +set xtrtol=2 +tran 0.1n 1000n +plot s1 s2+1.2 u1+2.4 d1+3.6 xlimit 100n 200n +plot v(vco) +.endc + +.end diff --git a/examples/xspice/pll/test_vco.cir b/examples/xspice/pll/test_vco.cir new file mode 100644 index 000000000..75b50ba03 --- /dev/null +++ b/examples/xspice/pll/test_vco.cir @@ -0,0 +1,149 @@ +VCO: 7 stage Ring-Osc. made of gain cells BSIM3 +* P.-H. Hsieh, J. Maxey, C.-K. K. Yang, IEEE JSSC, Sept. 2009, pp. 2488 - 2495 +* get frequency versus control voltage +* measure frequency of R.O. by fft + +.param vcc=3.3 +.csparam simtime=500n + +.include vco_sub.cir + +vdd dd 0 dc 'vcc' +vco cont 0 dc 2.5 +xvco buf digout cont dd ro_vco + +.option noacct + +.control +set xtrtol=2 +set dt = $curplot +set curplot = new +set curplottitle = "Frequency versus voltage" +set freq_volt = $curplot $ store its name to 'freq_volt' +setplot $freq_volt +let vcovec=vector(5) +let foscvec=vector(5) +setplot $dt +alter vco 0.5 +tran 0.1n $&simtime 0 +let {$freq_volt}.vcovec[0]=v(cont) +linearize buf +fft buf +* start meas at freq > 0 to skip large dc part +meas sp fosc MAX_AT buf from=1e3 to=1e9 +let {$freq_volt}.foscvec[0]=fosc +plot digout xlimit 140n 160n +reset +alter vco 1 +tran 0.1n $&simtime 0 +let {$freq_volt}.vcovec[1]=v(cont) +linearize buf +fft buf +meas sp fosc MAX_AT buf from=1e3 to=1e9 +let {$freq_volt}.foscvec[1]=fosc +plot digout xlimit 140n 160n +reset +alter vco 1.5 +tran 0.1n $&simtime 0 +let {$freq_volt}.vcovec[2]=v(cont) +linearize buf +fft buf +meas sp fosc MAX_AT buf from=1e3 to=1e9 +let {$freq_volt}.foscvec[2]=fosc +plot digout xlimit 140n 160n +reset +alter vco 2 +tran 0.1n $&simtime 0 +let {$freq_volt}.vcovec[3]=v(cont) +linearize buf +fft buf +meas sp fosc MAX_AT buf from=1e3 to=1e9 +let {$freq_volt}.foscvec[3]=fosc +plot digout xlimit 140n 160n +reset +alter vco 2.5 +tran 0.1n $&simtime 0 +let {$freq_volt}.vcovec[4]=v(cont) +linearize buf +fft buf +meas sp fosc MAX_AT buf from=1e3 to=1e9 +let {$freq_volt}.foscvec[4]=fosc +plot digout xlimit 140n 160n +plot tran1.buf tran3.buf tran5.buf tran7.buf tran9.buf xlimit 140n 160n +plot mag(sp2.buf) mag(sp4.buf) mag(sp6.buf) mag(sp8.buf) mag(sp10.buf) xlimit 100e6 1100e6 +setplot $freq_volt +settype frequency foscvec +settype voltage vcovec +plot foscvec vs vcovec +rusage +.endc + +*model = bsim3v3 +*Berkeley Spice Compatibility +* Lmin= .35 Lmax= 20 Wmin= .6 Wmax= 20 +.model N1 NMOS +*+version = 3.2.4 ++version = 3.3.0 ++Level= 8 ++Tnom=27.0 ++Nch= 2.498E+17 Tox=9E-09 Xj=1.00000E-07 ++Lint=9.36e-8 Wint=1.47e-7 ++Vth0= .6322 K1= .756 K2= -3.83e-2 K3= -2.612 ++Dvt0= 2.812 Dvt1= 0.462 Dvt2=-9.17e-2 ++Nlx= 3.52291E-08 W0= 1.163e-6 ++K3b= 2.233 ++Vsat= 86301.58 Ua= 6.47e-9 Ub= 4.23e-18 Uc=-4.706281E-11 ++Rdsw= 650 U0= 388.3203 wr=1 ++A0= .3496967 Ags=.1 B0=0.546 B1= 1 ++ Dwg = -6.0E-09 Dwb = -3.56E-09 Prwb = -.213 ++Keta=-3.605872E-02 A1= 2.778747E-02 A2= .9 ++Voff=-6.735529E-02 NFactor= 1.139926 Cit= 1.622527E-04 ++Cdsc=-2.147181E-05 ++Cdscb= 0 Dvt0w = 0 Dvt1w = 0 Dvt2w = 0 ++ Cdscd = 0 Prwg = 0 ++Eta0= 1.0281729E-02 Etab=-5.042203E-03 ++Dsub= .31871233 ++Pclm= 1.114846 Pdiblc1= 2.45357E-03 Pdiblc2= 6.406289E-03 ++Drout= .31871233 Pscbe1= 5000000 Pscbe2= 5E-09 Pdiblcb = -.234 ++Pvag= 0 delta=0.01 ++ Wl = 0 Ww = -1.420242E-09 Wwl = 0 ++ Wln = 0 Wwn = .2613948 Ll = 1.300902E-10 ++ Lw = 0 Lwl = 0 Lln = .316394 ++ Lwn = 0 ++kt1=-.3 kt2=-.051 ++At= 22400 ++Ute=-1.48 ++Ua1= 3.31E-10 Ub1= 2.61E-19 Uc1= -3.42e-10 ++Kt1l=0 Prt=764.3 + +.model P1 PMOS +*+version = 3.2.4 ++version = 3.3.0 ++Level= 8 ++Tnom=27.0 ++Nch= 3.533024E+17 Tox=9E-09 Xj=1.00000E-07 ++Lint=6.23e-8 Wint=1.22e-7 ++Vth0=-.6732829 K1= .8362093 K2=-8.606622E-02 K3= 1.82 ++Dvt0= 1.903801 Dvt1= .5333922 Dvt2=-.1862677 ++Nlx= 1.28e-8 W0= 2.1e-6 ++K3b= -0.24 Prwg=-0.001 Prwb=-0.323 ++Vsat= 103503.2 Ua= 1.39995E-09 Ub= 1.e-19 Uc=-2.73e-11 ++ Rdsw= 460 U0= 138.7609 ++A0= .4716551 Ags=0.12 ++Keta=-1.871516E-03 A1= .3417965 A2= 0.83 ++Voff=-.074182 NFactor= 1.54389 Cit=-1.015667E-03 ++Cdsc= 8.937517E-04 ++Cdscb= 1.45e-4 Cdscd=1.04e-4 ++ Dvt0w=0.232 Dvt1w=4.5e6 Dvt2w=-0.0023 ++Eta0= 6.024776E-02 Etab=-4.64593E-03 ++Dsub= .23222404 ++Pclm= .989 Pdiblc1= 2.07418E-02 Pdiblc2= 1.33813E-3 ++Drout= .3222404 Pscbe1= 118000 Pscbe2= 1E-09 ++Pvag= 0 ++kt1= -0.25 kt2= -0.032 prt=64.5 ++At= 33000 ++Ute= -1.5 ++Ua1= 4.312e-9 Ub1= 6.65e-19 Uc1= 0 ++Kt1l=0 + +.end diff --git a/examples/xspice/pll/vco_sub.cir b/examples/xspice/pll/vco_sub.cir new file mode 100644 index 000000000..830a33065 --- /dev/null +++ b/examples/xspice/pll/vco_sub.cir @@ -0,0 +1,66 @@ +* VCO: 7 stage Ring-Osc. made of gain cells BSIM3 +* P.-H. Hsieh, J. Maxey, C.-K. K. Yang, IEEE JSSC, Sept. 2009, pp. 2488 - 2495 +* automatically tune Vdd to achive a desired frequency of oscillation +* measure frequency of R.O. either by delay measurement or by fft + +***** ring oscillator as voltage controlled oscillator *************** +* name: ro_vco +* aout analog out +* dout digital out +* cont control voltage +* dd supply voltage + +.subckt ro_vco aout dout cont dd +* ignition circuit (not needed) +* feedback between in and out, pulse to help start oscillation +vin inm1 outp7 dc 0 +*vin inm1 outp7 dc 2.5 pulse 2.5 0 0.1n 5n 1 1 1 + +*vin2 inp1 outp7 dc -0.5 pulse -0.5 0 0.1n 5n 1 1 1 +vin2 inp1 outm7 dc 0 + + +vss ss 0 dc 0 +ve sub 0 dc 0 +vpe well 0 dc 3.3 + + +* gain cell +.subckt gaincell dd ss sub well co in- in+ out- out+ +mn1 out- in+ ss sub n1 w=2u l=0.35u AS=3p AD=3p PS=4u PD=4u +mn2 out- out+ ss sub n1 w=2u l=0.35u AS=3p AD=3p PS=4u PD=4u +mn3 out+ out- ss sub n1 w=2u l=0.35u AS=3p AD=3p PS=4u PD=4u +mn4 out+ in- ss sub n1 w=2u l=0.35u AS=3p AD=3p PS=4u PD=4u +mp1 out- co dd well p1 w=4u l=0.35u AS=7p AD=7p PS=6u PD=6u +mp2 out+ co dd well p1 w=4u l=0.35u AS=7p AD=7p PS=6u PD=6u +.ends gaincell + +* inverter +.subckt inv2 dd ss sub well in out +mn1 out in ss sub n1 w=6u l=0.35u AS=12p AD=12p PS=16u PD=16u +mp1 out in dd well p1 w=12u l=0.35u AS=24p AD=24p PS=28u PD=28u +.ends inv2 + +* inverter +.subckt inv1 dd ss sub well in out +mn1 out in ss sub n1 w=2u l=0.35u AS=3p AD=3p PS=4u PD=4u +mp1 out in dd well p1 w=4u l=0.35u AS=7p AD=7p PS=6u PD=6u +.ends inv1 + +* chain of 25 inverters + output buffer +xinv1 dd ss sub well cont inm1 inp1 outm1 outp1 gaincell +xinv2 dd ss sub well cont outp1 outm1 outm2 outp2 gaincell +xinv3 dd ss sub well cont outp2 outm2 outm3 outp3 gaincell +xinv4 dd ss sub well cont outp3 outm3 outm4 outp4 gaincell +xinv5 dd ss sub well cont outp4 outm4 outm5 outp5 gaincell +xinv6 dd ss sub well cont outp5 outm5 outm6 outp6 gaincell +xinv7 dd ss sub well cont outp6 outm6 outm7 outp7 gaincell +* analog out (two stage buffer) +xinv11 dd 0 sub well outm1 outm2 inv1 +xinv12 dd 0 sub well outm2 aout inv2 +cout aout 0 0.2pF +*digital out +abridge1 [aout] [dout] adc_buff +.model adc_buff adc_bridge(in_low = 'vcc*0.5' in_high = 'vcc*0.5') +.ends ro_vco +******************************************************************