From 7d81345a4bf9fb24af7efb68bff24325d8c5bee3 Mon Sep 17 00:00:00 2001
From: dwarning <dwarning>
Date: Mon, 15 May 2017 15:09:57 +0200
Subject: [PATCH] add spice gmin parameter to drain and source junction current

---
 src/spicelib/devices/adms/bsim6/admsva/bsim6.va | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/src/spicelib/devices/adms/bsim6/admsva/bsim6.va b/src/spicelib/devices/adms/bsim6/admsva/bsim6.va
index 4f57b3dc3..8151d8cb9 100755
--- a/src/spicelib/devices/adms/bsim6/admsva/bsim6.va
+++ b/src/spicelib/devices/adms/bsim6/admsva/bsim6.va
@@ -1857,6 +1857,8 @@ real AIGS_i, BIGS_i, CIGS_i, AIGD_i, BIGD_i, CIGD_i, POXEDGE_i, PIGCD_i;
 real DLCIG_i, DLCIGD_i, NTOX_i;
 real IGT_i;
 
+real _circuit_gmin;
+
 //stress effect
 real W_tmp_stress, tmp1_stress, kstress_u0, tmp1_stress_vth, kstress_vth0, ku0_temp;
 real Inv_sa, Inv_sb, Inv_saref, Inv_sbref, Inv_odref, rho_ref, Inv_od,rho;
@@ -4470,14 +4472,14 @@ end
 	// Diode Current and Capacitance
 `ifdef __RBODYMOD__
 	if(RBODYMOD != 0) begin
-		I(sbulk, `IntrinsicSource) <+ devsign * Ibs;
-		I(dbulk, `IntrinsicDrain)  <+ devsign * Ibd;
+		I(sbulk, `IntrinsicSource) <+ devsign * Ibs + _circuit_gmin*Vbs_jct;
+		I(dbulk, `IntrinsicDrain)  <+ devsign * Ibd + _circuit_gmin*Vbd_jct;
 		I(sbulk, `IntrinsicSource) <+ devsign * ddt(Qbs);
 		I(dbulk, `IntrinsicDrain)  <+ devsign * ddt(Qbd);
 	end else begin
 `endif
-		I(`IntrinsicBody, `IntrinsicSource) <+ devsign * Ibs;
-		I(`IntrinsicBody, `IntrinsicDrain)  <+ devsign * Ibd;
+		I(`IntrinsicBody, `IntrinsicSource) <+ devsign * Ibs + _circuit_gmin*Vbs_jct;
+		I(`IntrinsicBody, `IntrinsicDrain)  <+ devsign * Ibd + _circuit_gmin*Vbd_jct;
 		I(`IntrinsicBody, `IntrinsicSource) <+ devsign * ddt(Qbs);
 		I(`IntrinsicBody, `IntrinsicDrain)  <+ devsign * ddt(Qbd);
 `ifdef __RBODYMOD__