From 738ac4863cb52eaa8e3bc366f6f4e11f3bef444e Mon Sep 17 00:00:00 2001 From: Holger Vogt Date: Mon, 3 Jan 2022 21:57:38 +0100 Subject: [PATCH] Obtain memory and simulation time Add rusage information command --- examples/memristor/memristor_x.sp | 1 + examples/xspice/d_lut/mult4bit.spi | 1 + examples/xspice/d_source/PWMexample.net | 1 + examples/xspice/delay/analog-delay1.cir | 1 + examples/xspice/delta-sigma/delta-sigma-1.cir | 1 + examples/xspice/filesource/simple-filesource.cir | 1 + examples/xspice/state/state-machine.cir | 1 + 7 files changed, 7 insertions(+) diff --git a/examples/memristor/memristor_x.sp b/examples/memristor/memristor_x.sp index 98fbc6528..198cb979b 100644 --- a/examples/memristor/memristor_x.sp +++ b/examples/memristor/memristor_x.sp @@ -78,6 +78,7 @@ plot res vs time res1 vs tran1.time res2 vs tran2.time title 'Memristor with th plot res vs v(1) res1 vs tran1.v(1) res2 vs tran2.v(1) retraceplot title 'Memristor with threshold: resistance' * current through resistor for all plots versus voltage plot i(v1) vs v(1) tran1.i(v1) vs tran1.v(1) tran2.i(v1) vs tran2.v(1) retraceplot title 'Memristor with threshold: external current loops' +rusage .endc .end diff --git a/examples/xspice/d_lut/mult4bit.spi b/examples/xspice/d_lut/mult4bit.spi index acad1cec2..1aa501085 100644 --- a/examples/xspice/d_lut/mult4bit.spi +++ b/examples/xspice/d_lut/mult4bit.spi @@ -103,6 +103,7 @@ Xmult4 p7 p6 p5 p4 p3 p2 p1 p0 a3 a2 a1 a0 b3 b2 b1 b0 mult4bit .control tran 50us 12825us 25us +rusage linearize let aa = (((v(a3))*2 + v(a2))*2 + v(a1))*2 + v(a0) diff --git a/examples/xspice/d_source/PWMexample.net b/examples/xspice/d_source/PWMexample.net index a77712715..4ba2b148d 100644 --- a/examples/xspice/d_source/PWMexample.net +++ b/examples/xspice/d_source/PWMexample.net @@ -17,6 +17,7 @@ C1 0 1 10n .control save 33 44 1 tran 1us 50m +rusage wrdata $inputdir/fil2.dat V(33) v(44) V(1) plot v(44) V(1) xlimit 22.9m 23m .endc diff --git a/examples/xspice/delay/analog-delay1.cir b/examples/xspice/delay/analog-delay1.cir index f73b1e12d..9a31cbeec 100644 --- a/examples/xspice/delay/analog-delay1.cir +++ b/examples/xspice/delay/analog-delay1.cir @@ -39,6 +39,7 @@ Vc5 cntrl5 0 0 .control tran 1u 10m +rusage set xbrushwidth=2 plot v(in1) V(out1) title 'Const delay' plot v(in2) V(out2) title 'Variable delay' diff --git a/examples/xspice/delta-sigma/delta-sigma-1.cir b/examples/xspice/delta-sigma/delta-sigma-1.cir index b9c5e9cb3..23a498660 100644 --- a/examples/xspice/delta-sigma/delta-sigma-1.cir +++ b/examples/xspice/delta-sigma/delta-sigma-1.cir @@ -95,6 +95,7 @@ abridge22 [dclk xsinc.ddivndel1 xsinc.ddivndel2 dv] [acclk acset acres acin] dac .control save inp inm adaclout adaccout ; save memory space tran 0.1u $&simtime +rusage * analog out, scaled 'manually'; sinc filter counter; analog differential in plot 4.1*(adaclout-0.486) adaccout v(inp)-v(inm) ylimit -0.6 0.6 * modulator dig out diff --git a/examples/xspice/filesource/simple-filesource.cir b/examples/xspice/filesource/simple-filesource.cir index 708762499..d787759c2 100644 --- a/examples/xspice/filesource/simple-filesource.cir +++ b/examples/xspice/filesource/simple-filesource.cir @@ -22,6 +22,7 @@ Rload2 N_IN2 0 1k option NOINIT ACCT tran 1us 100us +rusage display plot allv .endc diff --git a/examples/xspice/state/state-machine.cir b/examples/xspice/state/state-machine.cir index 4f37914d3..663f14fee 100644 --- a/examples/xspice/state/state-machine.cir +++ b/examples/xspice/state/state-machine.cir @@ -29,6 +29,7 @@ a5 cntl clk var_clock .control tran 1us 10ms +rusage write spifsim.raw plot cntl out_msb+2 out_lsb+8 eprvcd n_one clk n_zero msb lsb > spifsim.vcd