From 6c52290193697b176aa31802051e1bc0d16ab5a5 Mon Sep 17 00:00:00 2001
From: rlar <rlar>
Date: Sun, 23 Jul 2017 21:03:29 +0200
Subject: [PATCH] bsimcmg, benchmark, TFIN FPITCH and L are instance parameters
 !

---
 bsimcmg_benchmark_test/ac.sp                 | 1 +
 bsimcmg_benchmark_test/gummel_n.sp           | 1 +
 bsimcmg_benchmark_test/gummel_p.sp           | 1 +
 bsimcmg_benchmark_test/invdc.sp              | 3 +++
 bsimcmg_benchmark_test/inverter_transient.sp | 3 +++
 bsimcmg_benchmark_test/modelcard.nmos        | 3 ---
 bsimcmg_benchmark_test/modelcard.pmos        | 3 ---
 bsimcmg_benchmark_test/noise.sp              | 1 +
 bsimcmg_benchmark_test/ringosc_17stg.sp      | 3 +++
 9 files changed, 13 insertions(+), 6 deletions(-)

diff --git a/bsimcmg_benchmark_test/ac.sp b/bsimcmg_benchmark_test/ac.sp
index 6c7e1e10d..775d3b290 100644
--- a/bsimcmg_benchmark_test/ac.sp
+++ b/bsimcmg_benchmark_test/ac.sp
@@ -16,6 +16,7 @@ vbs bulk 0 dc=0
 
 * --- Transistor ---
 m1 vout gate 0 bulk 0 nmos1 TFIN=15n L=30n NFIN=10 NRS=1 NRD=1
++ FPITCH  = 4.00E-08
 
 * --- Load ---
 rl supply vout r=2k
diff --git a/bsimcmg_benchmark_test/gummel_n.sp b/bsimcmg_benchmark_test/gummel_n.sp
index 1c3578768..8cf1445c1 100644
--- a/bsimcmg_benchmark_test/gummel_n.sp
+++ b/bsimcmg_benchmark_test/gummel_n.sp
@@ -17,6 +17,7 @@ vbulk bulk 0 dc=0.0
 * FIXME, parameter LSP has a different default !!
 *  see commit for bsimcmg_body.include
 m1 drain gate source bulk 0 nmos1 TFIN=15n L=30n NFIN=10 NRS=1 NRD=1
++ FPITCH  = 4.00E-08
 
 * --- DC Analysis ---
 .dc vdrain -0.1 0.1 0.001 vgate 0.0 1.0 0.2
diff --git a/bsimcmg_benchmark_test/gummel_p.sp b/bsimcmg_benchmark_test/gummel_p.sp
index 0583daa99..4f06f9a29 100644
--- a/bsimcmg_benchmark_test/gummel_p.sp
+++ b/bsimcmg_benchmark_test/gummel_p.sp
@@ -16,6 +16,7 @@ vbulk bulk 0 dc=0
 
 * --- Transistor ---
 m1 drain gate source bulk 0 pmos1 TFIN=15n L=30n NFIN=10 NRS=1 NRD=1
++ FPITCH  = 4.00E-08
 
 * --- DC Analysis ---
 .dc vdrain -0.1 0.1 0.001 vgate 0.0 -1.0 -0.2
diff --git a/bsimcmg_benchmark_test/invdc.sp b/bsimcmg_benchmark_test/invdc.sp
index a4bc8bb7f..083809c5e 100644
--- a/bsimcmg_benchmark_test/invdc.sp
+++ b/bsimcmg_benchmark_test/invdc.sp
@@ -15,7 +15,10 @@ vin   vi 0 dc=0.5
 * --- Inverter Subcircuit ---
 .subckt mg_inv vin vout vdd gnd
     mp1 vout vin vdd gnd 0 pmos1 TFIN=15n L=30n NFIN=10 NRS=1 NRD=1
++ FPITCH  = 4.00E-08
     mn1 vout vin gnd gnd 0 nmos1 TFIN=15n L=30n NFIN=10 NRS=1 NRD=1
++ FPITCH  = 4.00E-08
+
 .ends
 
 * --- Inverter ---
diff --git a/bsimcmg_benchmark_test/inverter_transient.sp b/bsimcmg_benchmark_test/inverter_transient.sp
index bb824ed69..76d61c134 100644
--- a/bsimcmg_benchmark_test/inverter_transient.sp
+++ b/bsimcmg_benchmark_test/inverter_transient.sp
@@ -15,7 +15,10 @@ vsig  vi  0 dc=0.5 sin (0.5 0.5 1MEG)
 * --- Inverter Subcircuit ---
 .subckt mg_inv vin vout vdd gnd
     mp1 vout vin vdd gnd 0 pmos1 TFIN=15n L=30n NFIN=10 ASEO=1.5e-14 ADEO=1.5e-14 NRS=1 NRD=1
++ FPITCH  = 4.00E-08
     mn1 vout vin gnd gnd 0 nmos1 TFIN=15n L=30n NFIN=10 ASEO=1.5e-14 ADEO=1.5e-14 NRS=1 NRD=1
++ FPITCH  = 4.00E-08
+
 .ends
 
 * --- Inverter ---
diff --git a/bsimcmg_benchmark_test/modelcard.nmos b/bsimcmg_benchmark_test/modelcard.nmos
index dbea9d5c0..de345b383 100644
--- a/bsimcmg_benchmark_test/modelcard.nmos
+++ b/bsimcmg_benchmark_test/modelcard.nmos
@@ -76,14 +76,12 @@
 + ETAMOB = 2
 + ETAQM  = 0.54
 + EU = 1.2
-+ FPITCH  = 4.00E-08
 + HFIN  = 3.00E-08
 + IGT  = 2.5
 + K1RSCE = 0
 + KSATIV = 2
 + KT1 = 0
 + KT1L = 0
-+ L  = 2.50E-08
 + LINT  = -2.00E-09
 + LPE0 = 0
 + LCDSCD = 5.00E-05
@@ -119,7 +117,6 @@
 + RTH0  = 0.225
 + TBGASUB = 0.000473
 + TBGBSUB = 636
-+ TFIN  = 1.40E-08
 + TGIDL  = -0.007
 + TMEXP  = 0
 + TNOM = 25
diff --git a/bsimcmg_benchmark_test/modelcard.pmos b/bsimcmg_benchmark_test/modelcard.pmos
index c1a040d59..2e4f9e34b 100644
--- a/bsimcmg_benchmark_test/modelcard.pmos
+++ b/bsimcmg_benchmark_test/modelcard.pmos
@@ -76,14 +76,12 @@
 + ETAMOB = 4
 + ETAQM  = 0.54
 + EU = 0.05
-+ FPITCH  = 4.00E-08
 + HFIN  = 3.00E-08
 + IGT  = 3.5
 + K1RSCE = 0
 + KSATIV = 1.592
 + KT1 = 0.08387
 + KT1L = 0
-+ L  = 2.50E-08
 + LINT  = -2.5E-09
 + LPE0 = 0
 + LCDSCD = 0
@@ -119,7 +117,6 @@
 + RTH0  = 0.15
 + TBGASUB = 0.000473
 + TBGBSUB = 636
-+ TFIN  = 1.40E-08
 + TGIDL  = -0.01
 + TMEXP  = 0
 + TNOM = 25
diff --git a/bsimcmg_benchmark_test/noise.sp b/bsimcmg_benchmark_test/noise.sp
index 799437f68..539224bb3 100644
--- a/bsimcmg_benchmark_test/noise.sp
+++ b/bsimcmg_benchmark_test/noise.sp
@@ -17,6 +17,7 @@ lbias 1 drain 1m
 cload drain 2 1m
 rload 2 0 R=1 noise=0
 X1 drain gate 0 bulk nmos1 TFIN=15n L=30n NFIN=10 NRS=1 NRD=1
++ FPITCH  = 4.00E-08
 
 * --- Analysis ---
 .op
diff --git a/bsimcmg_benchmark_test/ringosc_17stg.sp b/bsimcmg_benchmark_test/ringosc_17stg.sp
index db36feddf..f7204e9e0 100644
--- a/bsimcmg_benchmark_test/ringosc_17stg.sp
+++ b/bsimcmg_benchmark_test/ringosc_17stg.sp
@@ -15,7 +15,10 @@ vdd supply  0 dc=1.0
 * --- Inverter Subcircuit ---
 .subckt mg_inv vin vout vdd gnd
     mp1 vout vin vdd gnd 0 pmos1 TFIN=15n L=30n NFIN=10 ASEO=1.5e-14 ADEO=1.5e-14 NRS=1 NRD=1
++ FPITCH  = 4.00E-08
     mn1 vout vin gnd gnd 0 nmos1 TFIN=15n L=30n NFIN=10 ASEO=1.5e-14 ADEO=1.5e-14 NRS=1 NRD=1
++ FPITCH  = 4.00E-08
+
 .ends
 
 * --- 17 Stage Ring oscillator ---