diff --git a/examples/soi/inv_tr.sp b/examples/soi/inv_tr.sp
index d5cd80c98..b486374ba 100644
--- a/examples/soi/inv_tr.sp
+++ b/examples/soi/inv_tr.sp
@@ -1,4 +1,5 @@
-Mx  Drain Gate Source Back-gate(substrate) Body  Tx  W  L (body ommitted for FB)
+SOI Inverter
+* Mx  Drain Gate Source Back-gate(substrate) Body  Tx  W  L (body ommitted for FB)
 
 .include ./bsim4soi/nmos4p0.mod
 .include ./bsim4soi/pmos4p0.mod
@@ -7,13 +8,13 @@ Mx  Drain Gate Source Back-gate(substrate) Body  Tx  W  L (body ommitted for FB)
 Vpower VD 0 1.5
 Vgnd VS 0 0
 
-Vgate   Gate   VS PULSE(0v 1.5v 100ps 50ps 50ps 200ps 500ps)
+Vgate   Gate   VS DC 0 PULSE(0v 1.5v 100ps 50ps 50ps 200ps 500ps)
 
 *MN0 Out Gate VS VS VS N1 W=10u L=0.18u debug=1
 *MP0 Out Gate VD VS VD P1 W=20u L=0.18u debug=1
 
-MN0 Out Gate VS VS N1 W=10u L=0.18u
-MP0 Out Gate VD VS P1 W=20u L=0.18u
+MN0 Out Gate VS VS N1 W=10u L=0.18u Pd=11u Ps=11u
+MP0 Out Gate VD VS P1 W=20u L=0.18u Pd=11u Ps=11u
 
 .tran 3p 600ps
 .print tran v(gate) v(out)