From 5369c404429493f5cdde4a426aca9627e1192b58 Mon Sep 17 00:00:00 2001
From: rlar <rlar>
Date: Sun, 18 Mar 2018 18:14:47 +0100
Subject: [PATCH] bsimcmg, modify examples for ngspice

---
 examples/adms/bsimcmg/ac.sp                 | 10 ++++-
 examples/adms/bsimcmg/cfrgeo.sp             | 43 ++++++++++++-------
 examples/adms/bsimcmg/gummel_n.sp           | 23 ++++++++++-
 examples/adms/bsimcmg/gummel_p.sp           | 19 ++++++++-
 examples/adms/bsimcmg/idvdnmos.sp           | 38 +++++++++++++----
 examples/adms/bsimcmg/idvdpmos.sp           | 37 +++++++++++++----
 examples/adms/bsimcmg/idvgnmos.sp           | 25 +++++++----
 examples/adms/bsimcmg/idvgpmos.sp           | 37 +++++++++++++----
 examples/adms/bsimcmg/invdc.sp              | 11 +++--
 examples/adms/bsimcmg/inverter_transient.sp | 11 +++--
 examples/adms/bsimcmg/modelcard.nmos        |  2 +-
 examples/adms/bsimcmg/modelcard.nmos.1      |  2 +-
 examples/adms/bsimcmg/modelcard.pmos        |  2 +-
 examples/adms/bsimcmg/modelcard.pmos.1      |  2 +-
 examples/adms/bsimcmg/noise.sp              | 33 ++++++++++-----
 examples/adms/bsimcmg/rdsgeo.sp             | 46 ++++++++++++++-------
 examples/adms/bsimcmg/ringosc_17stg.sp      | 13 ++++--
 17 files changed, 268 insertions(+), 86 deletions(-)

diff --git a/examples/adms/bsimcmg/ac.sp b/examples/adms/bsimcmg/ac.sp
index 422769943..9c2fdb8b8 100644
--- a/examples/adms/bsimcmg/ac.sp
+++ b/examples/adms/bsimcmg/ac.sp
@@ -3,7 +3,7 @@
 
 .option abstol=1e-6 reltol=1e-6 post ingold
 
-.hdl "bsimcmg.va"
+*.hdl "bsimcmg.va"
 .include "modelcard.nmos"
 
 .param myvdd=1.0
@@ -14,7 +14,7 @@ vsig  gate  0 dc=0.5 ac=1
 vbs bulk 0 dc=0
 
 * --- Transistor ---
-X1 vout gate 0 bulk nmos1 TFIN=15n L=30n NFIN=10 NRS=1 NRD=1
+m1 vout gate 0 bulk nmos1 TFIN=15n L=30n NFIN=10 NRS=1 NRD=1
 
 * --- Load ---
 rl supply vout r=2k
@@ -31,5 +31,11 @@ cl supply vout c=10f
 *.alter
 *.param myvdd=2.0
 
+.control
+run
+plot vdb(vout)
+plot cph(vout)
+.endc
+
 .end
 
diff --git a/examples/adms/bsimcmg/cfrgeo.sp b/examples/adms/bsimcmg/cfrgeo.sp
index f73f306bf..1c17f7226 100644
--- a/examples/adms/bsimcmg/cfrgeo.sp
+++ b/examples/adms/bsimcmg/cfrgeo.sp
@@ -4,11 +4,11 @@
 .option abstol=1e-6 reltol=1e-6 post ingold
 .temp 27
 
-.hdl "bsimcmg.va"
+*.hdl "bsimcmg.va"
 
 .param hfin=30n
 
-.model nmos2 bsimcmg
+.model nmos2 NMOS level=72
 + DEVTYPE=1
 + CGEOMOD=2
 + HEPI=10n
@@ -28,22 +28,37 @@ vgs gate  0 dc=0
 vbs bulk  0 dc=0
 
 * --- Transistor ---
-X1 supply gate 0 bulk nmos2 TFIN=10n L=30n NFIN=1 FPITCH=20n LRSD=40n
-X2 supply gate 0 bulk nmos2 TFIN=10n L=30n NFIN=1 FPITCH=40n LRSD=40n
-X3 supply gate 0 bulk nmos2 TFIN=10n L=30n NFIN=1 FPITCH=60n LRSD=40n
-X4 supply gate 0 bulk nmos2 TFIN=10n L=30n NFIN=1 FPITCH=80n LRSD=40n
+M1 supply gate 0 bulk nmos2 TFIN=10n L=30n NFIN=1 FPITCH=20n LRSD=40n
+M2 supply gate 0 bulk nmos2 TFIN=10n L=30n NFIN=1 FPITCH=40n LRSD=40n
+M3 supply gate 0 bulk nmos2 TFIN=10n L=30n NFIN=1 FPITCH=60n LRSD=40n
+M4 supply gate 0 bulk nmos2 TFIN=10n L=30n NFIN=1 FPITCH=80n LRSD=40n
 
 * --- DC Analysis ---
-.dc vgs 0.0 1.0 1.5
-.print dc par'hfin' X1:CFGEO X2:CFGEO X3:CFGEO X4:CFGEO
+.dc vgs 0.0 1.0 0.1
+*.print dc par'hfin' M1:CFGEO M2:CFGEO M3:CFGEO M4:CFGEO
 
-.alter
-.param hfin=40n
+.control
+save @m1[CFGEO] @m2[CFGEO] @m3[CFGEO] @m4[CFGEO]
 
-.alter
-.param hfin=50n
+showmod #nmos2 : HFIN
+run
+plot @m1[CFGEO] @m2[CFGEO] @m3[CFGEO] @m4[CFGEO]
 
-.alter
-.param hfin=60n
+altermod nmos2 hfin = 40n
+showmod #nmos2 : HFIN
+run
+plot @m1[CFGEO] @m2[CFGEO] @m3[CFGEO] @m4[CFGEO]
+
+altermod nmos2 hfin = 50n
+showmod #nmos2 : HFIN
+run
+plot @m1[CFGEO] @m2[CFGEO] @m3[CFGEO] @m4[CFGEO]
+
+altermod nmos2 hfin = 60n
+showmod #nmos2 : HFIN
+run
+plot @m1[CFGEO] @m2[CFGEO] @m3[CFGEO] @m4[CFGEO]
+
+.endc
 
 .end
diff --git a/examples/adms/bsimcmg/gummel_n.sp b/examples/adms/bsimcmg/gummel_n.sp
index 0a936acb6..a870eb884 100644
--- a/examples/adms/bsimcmg/gummel_n.sp
+++ b/examples/adms/bsimcmg/gummel_n.sp
@@ -3,7 +3,7 @@
 
 .option abstol=1e-6 reltol=1e-6 post ingold
 
-.hdl "bsimcmg.va"
+*.hdl "bsimcmg.va"
 .include "modelcard.nmos"
 
 * --- Voltage Sources ---
@@ -14,7 +14,7 @@ vbulk bulk 0 dc=0.0
 
 
 * --- Transistor ---
-X1 drain gate source bulk nmos1 TFIN=15n L=30n NFIN=10 NRS=1 NRD=1
+m1 drain gate source bulk nmos1 TFIN=15n L=30n NFIN=10 NRS=1 NRD=1
 
 * --- DC Analysis ---
 .dc vdrain -0.1 0.1 0.001 vgate 0.0 1.0 0.2
@@ -25,4 +25,23 @@ X1 drain gate source bulk nmos1 TFIN=15n L=30n NFIN=10 NRS=1 NRD=1
 .probe dc gx4=deriv(gx3)
 .print dc par'ids' par'gx' par'gx2' par'gx3' par 'gx4'
 
+.control
+save @m1[VDSSAT]
+save @m1[GDS]
+run
+show all
+let ids = -i(vdrain)
+let gx = deriv(ids)
+let gx2 = deriv(gx)
+let gx3 = deriv(gx2)
+let gx4 = deriv(gx3)
+plot ids
+plot @m1[VDSSAT]
+plot @m1[GDS]
+plot gx
+plot gx2
+plot gx3
+plot gx4
+.endc
+
 .end
diff --git a/examples/adms/bsimcmg/gummel_p.sp b/examples/adms/bsimcmg/gummel_p.sp
index 399db7085..46677cadd 100644
--- a/examples/adms/bsimcmg/gummel_p.sp
+++ b/examples/adms/bsimcmg/gummel_p.sp
@@ -3,7 +3,7 @@
 
 .option abstol=1e-6 reltol=1e-6 post ingold
 
-.hdl "bsimcmg.va"
+*.hdl "bsimcmg.va"
 .include "modelcard.pmos"
 
 * --- Voltage Sources ---
@@ -14,7 +14,7 @@ vbulk bulk 0 dc=0
 
 
 * --- Transistor ---
-X1 drain gate source bulk pmos1 TFIN=15n L=30n NFIN=10 NRS=1 NRD=1
+m1 drain gate source bulk pmos1 TFIN=15n L=30n NFIN=10 NRS=1 NRD=1
 
 * --- DC Analysis ---
 .dc vdrain -0.1 0.1 0.001 vgate 0.0 -1.0 -0.2
@@ -25,4 +25,19 @@ X1 drain gate source bulk pmos1 TFIN=15n L=30n NFIN=10 NRS=1 NRD=1
 .probe dc gx4=deriv(gx3)
 .print dc par'ids' par'gx' par'gx2' par'gx3' par 'gx4'
 
+.control
+run
+let ids = -i(vdrain)
+let gx = deriv(ids)
+let gx2 = deriv(gx)
+let gx3 = deriv(gx2)
+let gx4 = deriv(gx3)
+plot ids
+plot gx
+plot gx2
+plot gx3
+plot gx4
+
+.endc
+
 .end
diff --git a/examples/adms/bsimcmg/idvdnmos.sp b/examples/adms/bsimcmg/idvdnmos.sp
index a02bcb480..e11416083 100644
--- a/examples/adms/bsimcmg/idvdnmos.sp
+++ b/examples/adms/bsimcmg/idvdnmos.sp
@@ -2,9 +2,8 @@
 *Id-Vd Characteristics for NMOS (T = 27 C)
 
 .option abstol=1e-6 reltol=1e-6 post ingold
-.temp -55
 
-.hdl "bsimcmg.va"
+*.hdl "bsimcmg.va"
 .include "modelcard.nmos.1"
 
 * --- Voltage Sources ---
@@ -13,7 +12,7 @@ vgs gate  0 dc=1.0
 vbs bulk  0 dc=0.2
 
 * --- Transistor ---
-X1 drain gate 0 bulk nmos1 TFIN=15n L=40n NFIN=10 NRS=1 NRD=1
+m1 drain gate 0 bulk nmos1 TFIN=15n L=40n NFIN=10 NRS=1 NRD=1
 
 * --- DC Analysis ---
 .dc vds 0 1 0.01 vgs 0 1.0 0.1
@@ -21,10 +20,35 @@ X1 drain gate 0 bulk nmos1 TFIN=15n L=40n NFIN=10 NRS=1 NRD=1
 .probe dc gds=deriv(ids)
 .print dc par'ids' par'gds'
 
-.alter
-.temp 27
+.control
+save @m1[gds]
+set temp = -55
+run
+let ids = -i(vds)
+let xgds = deriv(ids)
+plot ids
+plot xgds
+plot @m1[gds]
 
-.alter
-.temp 100
+save @m1[gds]
+set temp = 27
+run
+let ids = -i(vds)
+let xgds = deriv(ids)
+plot ids
+plot xgds
+plot @m1[gds]
+
+set temp = 100
+run
+let ids = -i(vds)
+let xgds = deriv(ids)
+plot ids
+plot xgds
+plot @m1[gds]
+
+*show all
+
+.endc
 
 .end
diff --git a/examples/adms/bsimcmg/idvdpmos.sp b/examples/adms/bsimcmg/idvdpmos.sp
index 8cd924102..db6f1f275 100644
--- a/examples/adms/bsimcmg/idvdpmos.sp
+++ b/examples/adms/bsimcmg/idvdpmos.sp
@@ -2,9 +2,8 @@
 *Id-Vd Characteristics for PMOS (T = 27 C)
 
 .option abstol=1e-6 reltol=1e-6 post ingold
-.temp -55
 
-.hdl "bsimcmg.va"
+*.hdl "bsimcmg.va"
 .include "modelcard.pmos.1"
 
 * --- Voltage Sources ---
@@ -13,7 +12,7 @@ vgs gate  0 dc=-1
 vbs bulk  0 dc=0
 
 * --- Transistor ---
-X1 drain gate 0 bulk pmos1 TFIN=15n L=40n NFIN=10 NRS=1 NRD=1
+m1 drain gate 0 bulk pmos1 TFIN=15n L=40n NFIN=10 NRS=1 NRD=1
 
 * --- DC Analysis ---
 .dc vds 0 -1 -0.01 vgs 0 -1.0 -0.1
@@ -21,10 +20,34 @@ X1 drain gate 0 bulk pmos1 TFIN=15n L=40n NFIN=10 NRS=1 NRD=1
 .probe dc gds=deriv(ids)
 .print dc par'ids' par'-gds'
 
-.alter
-.temp 27
+.control
 
-.alter
-.temp 100
+save @m1[gds]
+
+set temp = 27
+run
+let ids = i(vds)
+let xgds = deriv(ids)
+plot ids
+plot xgds
+plot @m1[gds]
+
+set temp = -55
+run
+let ids = i(vds)
+let xgds = deriv(ids)
+plot ids
+plot xgds
+plot @m1[gds]
+
+set temp = 100
+run
+let ids = i(vds)
+let xgds = deriv(ids)
+plot ids
+plot xgds
+plot @m1[gds]
+
+.endc
 
 .end
diff --git a/examples/adms/bsimcmg/idvgnmos.sp b/examples/adms/bsimcmg/idvgnmos.sp
index 3402ff114..7f0544ee4 100644
--- a/examples/adms/bsimcmg/idvgnmos.sp
+++ b/examples/adms/bsimcmg/idvgnmos.sp
@@ -2,9 +2,8 @@
 *Id-Vg Characteristics for NMOS (T = 27 C)
 
 .option abstol=1e-6 reltol=1e-6 post ingold
-.temp 27
 
-.hdl "bsimcmg.va"
+*.hdl "bsimcmg.va"
 .include "modelcard.nmos.1"
 
 * --- Voltage Sources ---
@@ -14,7 +13,7 @@ vbs bulk  0 dc=0
 vt   t    0 dc= 0
 
 * --- Transistor ---
-X1 supply gate 0 bulk  t nmos1 TFIN=15n L=30n NFIN=10 NRS=1 NRD=1
+m1 supply gate 0 bulk  t nmos1 TFIN=15n L=30n NFIN=10 NRS=1 NRD=1
 
 * --- DC Analysis ---
 .dc vgs -0.5 1.0 0.01 vds 0.05 1 0.95
@@ -22,10 +21,22 @@ X1 supply gate 0 bulk  t nmos1 TFIN=15n L=30n NFIN=10 NRS=1 NRD=1
 .probe dc par'-i(vbs)'
 .print dc i(X1.d)
 
-.alter 
-.temp -55
+.control
+set temp = 27
+run
+plot -i(vds)
+plot -i(vbs)
 
-.alter
-.temp 100
+set temp = -55
+run
+plot -i(vds)
+plot -i(vbs)
+
+set temp = 100
+run
+plot -i(vds)
+plot -i(vbs)
+
+.endc
 
 .end
diff --git a/examples/adms/bsimcmg/idvgpmos.sp b/examples/adms/bsimcmg/idvgpmos.sp
index cfaa4466f..f2a441b82 100644
--- a/examples/adms/bsimcmg/idvgpmos.sp
+++ b/examples/adms/bsimcmg/idvgpmos.sp
@@ -2,9 +2,8 @@
 *Id-Vg Characteristics for PMOS (T = 27 C)
 
 .option abstol=1e-6 reltol=1e-6 post ingold
-.temp -55
 
-.hdl "bsimcmg.va"
+*.hdl "bsimcmg.va"
 .include "modelcard.pmos.1"
 
 * --- Voltage Sources ---
@@ -13,7 +12,7 @@ vgs gate  0 dc=-1
 vbs bulk  0 dc=0
 
 * --- Transistor ---
-X1 supply gate 0 bulk pmos1 TFIN=15n L=30n NFIN=10 NRS=1 NRD=1
+m1 supply gate 0 bulk pmos1 TFIN=15n L=30n NFIN=10 NRS=1 NRD=1
 
 * --- DC Analysis ---
 .dc vgs 0.5 -1.0 -0.01 
@@ -21,10 +20,34 @@ X1 supply gate 0 bulk pmos1 TFIN=15n L=30n NFIN=10 NRS=1 NRD=1
 .probe dc gds=deriv(ids)
 .print dc par'ids' par'-gds'
 
-.alter
-.temp 27
+.control
 
-.alter
-.temp 100
+save @m1[gm]
+
+set temp = 27
+run
+let ids = i(vds)
+let xgds = deriv(ids)
+plot ids
+plot xgds
+plot @m1[gm]
+
+set temp = -55
+run
+let ids = i(vds)
+let xgds = deriv(ids)
+plot ids
+plot xgds
+plot @m1[gm]
+
+set temp = 100
+run
+let ids = i(vds)
+let xgds = deriv(ids)
+plot ids
+plot xgds
+plot @m1[gm]
+
+.endc
 
 .end
diff --git a/examples/adms/bsimcmg/invdc.sp b/examples/adms/bsimcmg/invdc.sp
index 8f7aea5e4..fa14b009b 100644
--- a/examples/adms/bsimcmg/invdc.sp
+++ b/examples/adms/bsimcmg/invdc.sp
@@ -3,7 +3,7 @@
 
 .option abstol=1e-6 reltol=1e-6 post ingold
 
-.hdl "bsimcmg.va"
+*.hdl "bsimcmg.va"
 .include "modelcard.nmos"
 .include "modelcard.pmos"
 
@@ -13,8 +13,8 @@ vin   vi 0 dc=0.5
 
 * --- Inverter Subcircuit ---
 .subckt mg_inv vin vout vdd gnd
-    Xp1 vout vin vdd gnd pmos1 TFIN=15n L=30n NFIN=10 NRS=1 NRD=1
-    Xn1 vout vin gnd gnd nmos1 TFIN=15n L=30n NFIN=10 NRS=1 NRD=1
+    mp1 vout vin vdd gnd pmos1 TFIN=15n L=30n NFIN=10 NRS=1 NRD=1
+    mn1 vout vin gnd gnd nmos1 TFIN=15n L=30n NFIN=10 NRS=1 NRD=1
 .ends
 
 * --- Inverter ---
@@ -25,4 +25,9 @@ Xinv1  vi vo supply 0 mg_inv
 
 .print dc v(vi) v(vo)
 
+.control
+run
+plot v(vi) v(vo)
+.endc
+
 .end
diff --git a/examples/adms/bsimcmg/inverter_transient.sp b/examples/adms/bsimcmg/inverter_transient.sp
index a0d1d73c2..fa0bdc58f 100644
--- a/examples/adms/bsimcmg/inverter_transient.sp
+++ b/examples/adms/bsimcmg/inverter_transient.sp
@@ -3,7 +3,7 @@
 
 .option abstol=1e-6 reltol=1e-6 post ingold
 
-.hdl "bsimcmg.va"
+*.hdl "bsimcmg.va"
 .include "modelcard.nmos"
 .include "modelcard.pmos"
 
@@ -13,8 +13,8 @@ vsig  vi  0 dc=0.5 sin (0.5 0.5 1MEG)
 
 * --- Inverter Subcircuit ---
 .subckt mg_inv vin vout vdd gnd
-    Xp1 vout vin vdd gnd pmos1 TFIN=15n L=30n NFIN=10 ASEO=1.5e-14 ADEO=1.5e-14 NRS=1 NRD=1
-    Xn1 vout vin gnd gnd nmos1 TFIN=15n L=30n NFIN=10 ASEO=1.5e-14 ADEO=1.5e-14 NRS=1 NRD=1
+    mp1 vout vin vdd gnd pmos1 TFIN=15n L=30n NFIN=10 ASEO=1.5e-14 ADEO=1.5e-14 NRS=1 NRD=1
+    mn1 vout vin gnd gnd nmos1 TFIN=15n L=30n NFIN=10 ASEO=1.5e-14 ADEO=1.5e-14 NRS=1 NRD=1
 .ends
 
 * --- Inverter ---
@@ -29,4 +29,9 @@ Xinv5  4 vo supply 0 mg_inv
 
 .print tran v(vi) v(vo)
 
+.control
+run
+plot v(vi) v(vo)
+.endc
+
 .end
diff --git a/examples/adms/bsimcmg/modelcard.nmos b/examples/adms/bsimcmg/modelcard.nmos
index fda0dd386..9f8c8f4d5 100644
--- a/examples/adms/bsimcmg/modelcard.nmos
+++ b/examples/adms/bsimcmg/modelcard.nmos
@@ -5,7 +5,7 @@
 ** other purposes except for benchmarking the implementation of BSIM-MG
 ** against BSIM Team's standard results
 
-.model nmos1 bsimcmg
+.model nmos1 NMOS level=72
 + BULKMOD = 1
 + CGEOMOD = 0
 + TYPE = 1
diff --git a/examples/adms/bsimcmg/modelcard.nmos.1 b/examples/adms/bsimcmg/modelcard.nmos.1
index a6c4e39f9..c0a32d6b2 100644
--- a/examples/adms/bsimcmg/modelcard.nmos.1
+++ b/examples/adms/bsimcmg/modelcard.nmos.1
@@ -5,7 +5,7 @@
 ** other purposes except for benchmarking the implementation of BSIM-MG
 ** against BSIM Team's standard results
 
-.model nmos1 bsimcmg
+.model nmos1 NMOS level=72
 + AGIDL = 50.00f 
 + AGISL = 50.00f 
 + AIGBINV = 11.10m 
diff --git a/examples/adms/bsimcmg/modelcard.pmos b/examples/adms/bsimcmg/modelcard.pmos
index 11ff8ace1..75e5d6975 100644
--- a/examples/adms/bsimcmg/modelcard.pmos
+++ b/examples/adms/bsimcmg/modelcard.pmos
@@ -5,7 +5,7 @@
 ** other purposes except for benchmarking the implementation of BSIM-MG
 ** against BSIM Team's standard results
 
-.model pmos1 bsimcmg
+.model pmos1 PMOS level=72
 + BULKMOD = 1
 + CGEOMOD = 0
 + TYPE = 0
diff --git a/examples/adms/bsimcmg/modelcard.pmos.1 b/examples/adms/bsimcmg/modelcard.pmos.1
index 4cf06281f..795193881 100644
--- a/examples/adms/bsimcmg/modelcard.pmos.1
+++ b/examples/adms/bsimcmg/modelcard.pmos.1
@@ -5,7 +5,7 @@
 ** other purposes except for benchmarking the implementation of BSIM-MG
 ** against BSIM Team's standard results
 
-.model pmos1 bsimcmg
+.model pmos1 PMOS level=72
 + AGIDL =3.000p
 + AGISL =3.000p
 + AIGBINV =11.10m
diff --git a/examples/adms/bsimcmg/noise.sp b/examples/adms/bsimcmg/noise.sp
index 799437f68..588cbbeb1 100644
--- a/examples/adms/bsimcmg/noise.sp
+++ b/examples/adms/bsimcmg/noise.sp
@@ -4,7 +4,7 @@
 .option abstol=1e-6 reltol=1e-6 post ingold
 .temp 27
 
-.hdl "bsimcmg.va"
+*.hdl "bsimcmg.va"
 .include "modelcard.nmos"
 
 * --- Voltage Sources ---
@@ -16,16 +16,29 @@ vbs bulk 0 dc=0v
 lbias 1 drain 1m
 cload drain 2 1m
 rload 2 0 R=1 noise=0
-X1 drain gate 0 bulk nmos1 TFIN=15n L=30n NFIN=10 NRS=1 NRD=1
+m1 drain gate 0 bulk nmos1 TFIN=15n L=30n NFIN=10 NRS=1 NRD=1
 
 * --- Analysis ---
-.op
-*.dc vgs -0.5 1.5 0.01
-*.print dc i(lbias)
-.ac dec 11 1k 100g
-.noise v(drain) vgs 1
-*.print ac i(cload)
-.print ac v(drain)
-.print noise inoise onoise
+*.op
+**.dc vgs -0.5 1.5 0.01
+**.print dc i(lbias)
+*.ac dec 11 1k 100g
+*.noise v(drain) vgs 1
+**.print ac i(cload)
+*.print ac v(drain)
+*.print noise inoise onoise
+
+.control
+op
+
+ac dec 11 1k 100g
+plot vdb(drain)
+
+noise v(drain) vgs dec 11 1k 100g
+print all
+echo "silence in the studio, no noise today"
+
+.endc
+
 .end
 
diff --git a/examples/adms/bsimcmg/rdsgeo.sp b/examples/adms/bsimcmg/rdsgeo.sp
index d9b3d9b05..84f9e8f00 100644
--- a/examples/adms/bsimcmg/rdsgeo.sp
+++ b/examples/adms/bsimcmg/rdsgeo.sp
@@ -4,9 +4,9 @@
 .option abstol=1e-6 reltol=1e-6 post ingold
 .temp 27
 
-.hdl "bsimcmg.va"
+*.hdl "bsimcmg.va"
 
-.model nmos2 bsimcmg
+.model nmos2 NMOS level=72
 + DEVTYPE=1
 + RGEOMOD=1
 + HEPI=15n
@@ -18,7 +18,7 @@
 + NSD=2.0e+26
 + LINT = 0
 
-.model pmos2 bsimcmg
+.model pmos2 PMOS level=72
 + DEVTYPE=0
 + RGEOMOD=1
 + HEPI=15n
@@ -38,21 +38,39 @@ vgs gate  0 dc=0
 vbs bulk  0 dc=0
 
 * --- Transistor ---
-Xn1 supply gate 0 bulk nmos2 TFIN=15n L=30n NFIN=10 FPITCH=fp SDTERM=0 LRSD=20n
-Xn2 supply gate 0 bulk nmos2 TFIN=15n L=30n NFIN=10 FPITCH=fp SDTERM=0 LRSD=40n
-Xn3 supply gate 0 bulk nmos2 TFIN=15n L=30n NFIN=10 FPITCH=fp SDTERM=0 LRSD=60n
-Xn4 supply gate 0 bulk nmos2 TFIN=15n L=30n NFIN=10 FPITCH=fp SDTERM=0 LRSD=80n
-Xp1 supply gate 0 bulk pmos2 TFIN=15n L=30n NFIN=10 FPITCH=fp SDTERM=0 LRSD=20n
-Xp2 supply gate 0 bulk pmos2 TFIN=15n L=30n NFIN=10 FPITCH=fp SDTERM=0 LRSD=40n
-Xp3 supply gate 0 bulk pmos2 TFIN=15n L=30n NFIN=10 FPITCH=fp SDTERM=0 LRSD=60n
-Xp4 supply gate 0 bulk pmos2 TFIN=15n L=30n NFIN=10 FPITCH=fp SDTERM=0 LRSD=80n
+mn1 supply gate 0 bulk nmos2 TFIN=15n L=30n NFIN=10 FPITCH=fp SDTERM=0 LRSD=20n
+mn2 supply gate 0 bulk nmos2 TFIN=15n L=30n NFIN=10 FPITCH=fp SDTERM=0 LRSD=40n
+mn3 supply gate 0 bulk nmos2 TFIN=15n L=30n NFIN=10 FPITCH=fp SDTERM=0 LRSD=60n
+mn4 supply gate 0 bulk nmos2 TFIN=15n L=30n NFIN=10 FPITCH=fp SDTERM=0 LRSD=80n
+mp1 supply gate 0 bulk pmos2 TFIN=15n L=30n NFIN=10 FPITCH=fp SDTERM=0 LRSD=20n
+mp2 supply gate 0 bulk pmos2 TFIN=15n L=30n NFIN=10 FPITCH=fp SDTERM=0 LRSD=40n
+mp3 supply gate 0 bulk pmos2 TFIN=15n L=30n NFIN=10 FPITCH=fp SDTERM=0 LRSD=60n
+mp4 supply gate 0 bulk pmos2 TFIN=15n L=30n NFIN=10 FPITCH=fp SDTERM=0 LRSD=80n
 
 * --- DC Analysis ---
-.dc vgs 0.0 1.0 2.0
+.dc vgs 0.0 1.0 0.1
 .print dc Xn1:RSGEO Xn2:RSGEO Xn3:RSGEO Xn4:RSGEO
 .print dc Xp1:RSGEO Xp2:RSGEO Xp3:RSGEO Xp4:RSGEO
 
-.alter 
-.param fp=90n
+.control
+save @Mn1[RSGEO] @Mn2[RSGEO] @Mn3[RSGEO] @Mn4[RSGEO]
+save @Mp1[RSGEO] @Mp2[RSGEO] @Mp3[RSGEO] @Mp4[RSGEO]
+run
+plot @Mn1[RSGEO] @Mn2[RSGEO] @Mn3[RSGEO] @Mn4[RSGEO]
+plot @Mp1[RSGEO] @Mp2[RSGEO] @Mp3[RSGEO] @Mp4[RSGEO]
+
+alter @mn1[FPITCH] = 90n
+alter @mn2[FPITCH] = 90n
+alter @mn3[FPITCH] = 90n
+alter @mn4[FPITCH] = 90n
+alter @mp1[FPITCH] = 90n
+alter @mp2[FPITCH] = 90n
+alter @mp3[FPITCH] = 90n
+alter @mp4[FPITCH] = 90n
+run
+plot @Mn1[RSGEO] @Mn2[RSGEO] @Mn3[RSGEO] @Mn4[RSGEO]
+plot @Mp1[RSGEO] @Mp2[RSGEO] @Mp3[RSGEO] @Mp4[RSGEO]
+
+.endc
 
 .end
diff --git a/examples/adms/bsimcmg/ringosc_17stg.sp b/examples/adms/bsimcmg/ringosc_17stg.sp
index 40c14ee53..affafd7c6 100644
--- a/examples/adms/bsimcmg/ringosc_17stg.sp
+++ b/examples/adms/bsimcmg/ringosc_17stg.sp
@@ -4,7 +4,7 @@
 *.options abstol=1e-6 reltol=1e-6 post ingold
 .options abstol=1e-6 reltol=1e-6 post ingold dcon=1
 
-.hdl "bsimcmg.va"
+*.hdl "bsimcmg.va"
 .include "modelcard.nmos"
 .include "modelcard.pmos"
 
@@ -13,8 +13,8 @@ vdd supply  0 dc=1.0
 
 * --- Inverter Subcircuit ---
 .subckt mg_inv vin vout vdd gnd
-    Xp1 vout vin vdd gnd pmos1 TFIN=15n L=30n NFIN=10 ASEO=1.5e-14 ADEO=1.5e-14 NRS=1 NRD=1
-    Xn1 vout vin gnd gnd nmos1 TFIN=15n L=30n NFIN=10 ASEO=1.5e-14 ADEO=1.5e-14 NRS=1 NRD=1
+    mp1 vout vin vdd gnd pmos1 TFIN=15n L=30n NFIN=10 ASEO=1.5e-14 ADEO=1.5e-14 NRS=1 NRD=1
+    mn1 vout vin gnd gnd nmos1 TFIN=15n L=30n NFIN=10 ASEO=1.5e-14 ADEO=1.5e-14 NRS=1 NRD=1
 .ends
 
 * --- 17 Stage Ring oscillator ---
@@ -37,7 +37,7 @@ Xinv16 16 17 supply 0 mg_inv
 Xinv17 17  1 supply 0 mg_inv
 
 * --- Initial Condition ---
-.ic  1=1
+.ic  v(1)=1
 
 .tran 1p 1n
 
@@ -48,4 +48,9 @@ Xinv17 17  1 supply 0 mg_inv
 .measure tran period param'(t2-t1)/3'
 .measure tran delay_per_stage param'period/34'
 
+.control
+run
+plot v(1)
+.endc
+
 .end