From 4b3de8e3bb6a5fe9c41f60e0819bccc67aef4ddf Mon Sep 17 00:00:00 2001 From: Holger Vogt Date: Mon, 5 May 2025 15:11:05 +0200 Subject: [PATCH] Enable a pulse width (widths of its top) of 0 to obtain true triangular waveforms --- src/spicelib/devices/vsrc/vsrcacct.c | 2 +- src/spicelib/devices/vsrc/vsrcload.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/spicelib/devices/vsrc/vsrcacct.c b/src/spicelib/devices/vsrc/vsrcacct.c index df890ed76..cd7d1111a 100644 --- a/src/spicelib/devices/vsrc/vsrcacct.c +++ b/src/spicelib/devices/vsrc/vsrcacct.c @@ -65,7 +65,7 @@ VSRCaccept(CKTcircuit *ckt, GENmodel *inModel) && here->VSRCcoeffs[4] != 0.0 ? here->VSRCcoeffs[4] : ckt->CKTstep; PW = here->VSRCfunctionOrder > 5 - && here->VSRCcoeffs[5] != 0.0 + && here->VSRCcoeffs[5] >= 0.0 ? here->VSRCcoeffs[5] : ckt->CKTfinalTime; PER = here->VSRCfunctionOrder > 6 && here->VSRCcoeffs[6] != 0.0 diff --git a/src/spicelib/devices/vsrc/vsrcload.c b/src/spicelib/devices/vsrc/vsrcload.c index c74c9a756..0ecf99c25 100644 --- a/src/spicelib/devices/vsrc/vsrcload.c +++ b/src/spicelib/devices/vsrc/vsrcload.c @@ -112,7 +112,7 @@ VSRCload(GENmodel *inModel, CKTcircuit *ckt) && here->VSRCcoeffs[4] != 0.0 ? here->VSRCcoeffs[4] : ckt->CKTstep; PW = here->VSRCfunctionOrder > 5 - && here->VSRCcoeffs[5] != 0.0 + && here->VSRCcoeffs[5] >= 0.0 ? here->VSRCcoeffs[5] : ckt->CKTfinalTime; PER = here->VSRCfunctionOrder > 6 && here->VSRCcoeffs[6] != 0.0