From 45c88edb7742465ee56df4024499a5773c132a4a Mon Sep 17 00:00:00 2001 From: Brian Taylor Date: Mon, 16 May 2022 19:46:54 -0700 Subject: [PATCH] All-digital U* device examples. No a/d or d/a interfaces on the subcircuits. --- examples/p-to-n-examples/ex4.cir | 84 +++++++++++++++++++ examples/p-to-n-examples/ex4.stim | 13 +++ examples/p-to-n-examples/ex5.cir | 131 ++++++++++++++++++++++++++++++ examples/p-to-n-examples/ex5.stim | 17 ++++ 4 files changed, 245 insertions(+) create mode 100644 examples/p-to-n-examples/ex4.cir create mode 100644 examples/p-to-n-examples/ex4.stim create mode 100644 examples/p-to-n-examples/ex5.cir create mode 100644 examples/p-to-n-examples/ex5.stim diff --git a/examples/p-to-n-examples/ex4.cir b/examples/p-to-n-examples/ex4.cir new file mode 100644 index 000000000..b4e046a02 --- /dev/null +++ b/examples/p-to-n-examples/ex4.cir @@ -0,0 +1,84 @@ +Full adder pspice + +* ----------------------------------------------------------- 74LV86A ------ +* Quad 2-Input Exclusive-Or Gate +* +* TI PDF File +* bss 2/24/03 +* +.SUBCKT 74LV86A 1A 1B 1Y ++ optional: DPWR_3V=$G_DPWR_3V DGND_3V=$G_DGND_3V ++ params: MNTYMXDLY=0 IO_LEVEL=0 + +U1 xor DPWR_3V DGND_3V ++ 1A 1B 1Y ++ DLY_LV86 IO_LV-A MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + +.model DLY_LV86 ugate (tplhTY=7.4ns tplhMX=14.5ns tphlTY=7.4ns tphlMX=14.5ns) + +.ENDS 74LV86A + +* ----------------------------------------------------------- 74LV08A ------ +* Quad 2-Input And Gate +* +* TI PDF File +* bss 2/21/03 +* +.SUBCKT 74LV08A 1A 1B 1Y ++ optional: DPWR_3V=$G_DPWR_3V DGND_3V=$G_DGND_3V ++ params: MNTYMXDLY=0 IO_LEVEL=0 + +U1 and(2) DPWR_3V DGND_3V ++ 1A 1B 1Y ++ DLY_LV08 IO_LV-A MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + +.model DLY_LV08 ugate (tplhTY=7.5ns tplhMX=12.3ns tphlTY=7.5ns tphlMX=12.3ns) + +.ENDS 74LV08A + +* ----------------------------------------------------------- 74LV32A ------ +* Quad 2-Input Or Gate +* +* TI PDF File +* bss 2/24/03 +* +.SUBCKT 74LV32A 1A 1B 1Y ++ optional: DPWR_3V=$G_DPWR_3V DGND_3V=$G_DGND_3V ++ params: MNTYMXDLY=0 IO_LEVEL=0 + +U1 or(2) DPWR_3V DGND_3V ++ 1A 1B 1Y ++ DLY_LV32 IO_LV-A MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + +.model DLY_LV32 ugate ( ++ tplhTY=6.9ns tplhMX=11.4ns tphlTY=6.9ns tphlMX=11.4ns) + +.ENDS 74LV32A + +.subckt hadd a b sum carry +x1_xor a b sum 74lv86a +x2_and a b carry 74lv08a +.ends hadd + +.subckt fadd a b cin sum cout +x1_ha a b 1 2 hadd +x2_ha 1 cin sum 3 hadd +x3_or 3 2 cout 74lv32a +.ends fadd + +x1 a b cin sum cout fadd +a2 [a b cin] input_vec1 +.model input_vec1 d_source(input_file = "ex4.stim") + +.tran 0.5ns 1650ns 0 +.save all +.control +listing expand +run +display +edisplay +eprint a b cin sum cout +*plot cout sum +quit +.endc +.end diff --git a/examples/p-to-n-examples/ex4.stim b/examples/p-to-n-examples/ex4.stim new file mode 100644 index 000000000..9bf9b1e20 --- /dev/null +++ b/examples/p-to-n-examples/ex4.stim @@ -0,0 +1,13 @@ +* T a b C +* i i +* m n +* e +0.000 0s 0s 0s +2.0e-7 0s 0s 1s +4.0e-7 0s 1s 0s +6.0e-7 0s 1s 1s +8.0e-7 1s 0s 0s +10.0e-7 1s 0s 1s +12.0e-7 1s 1s 0s +14.0e-7 1s 1s 1s +16.0e-7 0s 0s 0s diff --git a/examples/p-to-n-examples/ex5.cir b/examples/p-to-n-examples/ex5.cir new file mode 100644 index 000000000..7c05aa588 --- /dev/null +++ b/examples/p-to-n-examples/ex5.cir @@ -0,0 +1,131 @@ +Some dff + +* ----------------------------------------------------------- 74LV374A ------ +* Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputs +* +* TI PDF File +* bss 2/28/03 +* +.SUBCKT 74LV374A OEBAR CLK 1D 2D 3D 4D 5D 6D 7D 8D 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q ++ optional: DPWR_3V=$G_DPWR_3V DGND_3V=$G_DGND_3V ++ params: MNTYMXDLY=0 IO_LEVEL=0 + +U1 dff(8) DPWR_3V DGND_3V ++ $D_HI $D_HI CLK ++ 1D 2D 3D 4D 5D 6D 7D 8D ++ $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC ++ 1QB 2QB 3QB 4QB 5QB 6QB 7QB 8QB ++ DLY1_LV374 IO_LV-A MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + +U2 inv DPWR_3V DGND_3V ++ OEBAR OE ++ D0_GATE IO_LV-A MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + +U3 inv3a(8) DPWR_3V DGND_3V ++ 1QB 2QB 3QB 4QB 5QB 6QB 7QB 8QB ++ OE ++ 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q ++ DLY2_LV374 IO_LV-A MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + +.model DLY1_LV374 ueff(tpclkqhlTY=8.3ns tpclkqhlMX=16.2ns tpclkqlhTY=8.3ns tpclkqlhMX=16.2ns ++ twclklMN=5ns twclkhMN=5ns tsudclkMN=4.5ns thdclkMN=2ns) + +.model DLY2_LV374 utgate (tplzTY=5.9ns tplzMX=14ns tphzTY=5.9ns tphzMX=14ns ++ tpzlTY=7.7ns tpzlMX=14.5ns tpzhTY=7.7ns tpzhMX=14.5ns) + +.ENDS 74LV374A + +* ----------------------------------------------------------- 74LV574A ------ +* Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputs +* +* TI PDF File +* bss 2/28/03 +* +.SUBCKT 74LV574A OEBAR CLK 1D 2D 3D 4D 5D 6D 7D 8D ++ 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q ++ optional: DPWR_3V=$G_DPWR_3V DGND_3V=$G_DGND_3V ++ params: MNTYMXDLY=0 IO_LEVEL=0 + +U1 inv DPWR_3V DGND_3V ++ OEBAR OE ++ D0_GATE IO_LV-A MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + +U2 dff(8) DPWR_3V DGND_3V ++ $D_HI $D_HI CLK ++ 1D 2D 3D 4D 5D 6D 7D 8D ++ Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 ++ $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC ++ DLY_LV574 IO_LV-A MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + +U3 buf3a(8) DPWR_3V DGND_3V ++ Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 ++ OE ++ 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q ++ DLY_LV574Z IO_LV-A MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + +.model DLY_LV574 ueff(tpclkqhlTY=8.1ns tpclkqhlMX=16.7ns tpclkqlhTY=8.1ns tpclkqlhMX=16.7ns ++ twclklMN=5ns twclkhMN=5ns tsudclkMN=3.5ns thdclkMN=1.5ns) + +.model DLY_LV574Z utgate (tpzhTY=7.7ns tpzhMX=16.3ns tpzlTY=7.7ns tpzlMX=16.3ns ++ tphzTY=6.1ns tphzMX=15ns tplzTY=6.1ns tplzMX=15ns) + +.ENDS 74LV574A + + +x1 oeb clk 1in 2in 3in 4in 5in 6in 7in 8in o1 o2 o3 o4 o5 o6 o7 o8 74lv374a +x2 oeb clk 1in 2in 3in 4in 5in 6in 7in 8in q1 q2 q3 q4 q5 q6 q7 q8 74lv574a + +a1 [oeb clk 1in 2in 3in 4in 5in 6in 7in 8in] input_vec1 +.model input_vec1 d_source(input_file = "ex5.stim") + +x3 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 74als242b + +* ----------------------------------------------------------- 74ALS242B ------ +* Quad Bus Transceivers With 3-State Outputs +* +* The ALS/AS Logic Data Book, 1986, TI Pages 2-271 to 2-276 +* jds 5/25/94 +* +.SUBCKT 74ALS242B GABBAR GBA A1 A2 A3 A4 B1 B2 B3 B4 ++ optional: DPWR=$G_DPWR DGND=$G_DGND ++ params: MNTYMXDLY=0 IO_LEVEL=0 + +uf0 inv DPWR DGND ++ GABBAR GAB ++ D0_GATE IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + +uf1 inv3a(4) DPWR DGND ++ A1 A2 A3 A4 ++ GAB ++ B1 B2 B3 B4 ++ DLY_MOD IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + +uf2 inv3a(4) DPWR DGND ++ B1 B2 B3 B4 ++ GBA ++ A1 A2 A3 A4 ++ DLY_MOD IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + +.model DLY_MOD utgate (TPLHMN=-1 TPLHTY=5ns TPLHMX=-1 ++ TPHLMN=-1 TPHLTY=5ns TPHLMX=-1 ++ TPZLMN=-1 TPZLTY=11ns TPZLMX=-1 ++ TPZHMN=-1 TPZHTY=10ns TPZHMX=-1 ++ TPLZMN=-1 TPLZTY=5ns TPLZMX=-1 ++ TPHZMN=-1 TPHZTY=6ns TPHZMX=-1) + +.ENDS 74ALS242B + +.tran 0.1ns 150ns 0 +.save all + +.control +listing expand +run +*display +*edisplay +eprint o1 o2 o3 o4 o5 o6 o7 o8 +eprint q1 q2 q3 q4 q5 q6 q7 q8 +*plot q4 o6 +quit +.endc +.end diff --git a/examples/p-to-n-examples/ex5.stim b/examples/p-to-n-examples/ex5.stim new file mode 100644 index 000000000..6d6de87f6 --- /dev/null +++ b/examples/p-to-n-examples/ex5.stim @@ -0,0 +1,17 @@ +* e c 1 2 3 4 5 6 7 7 +* n k i i i i i i i i +0.000 0s 0s 1s 1s 0s 0s 1s 1s 0s 0s +5.0ns 0s 1s 1s 1s 0s 0s 1s 1s 0s 0s +10.0ns 0s 0s 0s 0s 1s 1s 0s 0s 1s 1s +20.0ns 0s 1s 0s 0s 1s 1s 0s 0s 1s 1s +30.0ns 1s 0s 0s 0s 1s 1s 0s 0s 1s 1s +45.0ns 0s 0s 0s 0s 0s 0s 1s 1s 1s 1s +55.0ns 0s 1s 0s 0s 1s 0s 1s 0s 1s 1s +65.0ns 0s 0s 0s 0s 0s 0s 0s 0s 0s 0s +75.0ns 0s 1s 0s 0s 0s 0s 0s 0s 0s 0s +85.0ns 0s 0s 0s 0s 0s 0s 0s 0s 0s 0s +90.0ns 0s 0s 1s 1s 1s 1s 0s 0s 0s 0s +95.0ns 0s 1s 1s 1s 1s 1s 0s 0s 0s 0s +105.0ns 0s 0s 0s 0s 0s 0s 1s 1s 1s 1s +115.0ns 0s 1s 0s 0s 0s 0s 1s 1s 1s 1s +125.0ns 0s 0s 0s 0s 0s 0s 1s 1s 1s 1s