From 454f2bfb64d5dea14942be92b50b41771efab117 Mon Sep 17 00:00:00 2001
From: rlar <rlar>
Date: Sun, 25 Feb 2018 12:01:19 +0100
Subject: [PATCH] trunc-1.cir, testcase, negative, no truncation at all ?

---
 trunc-1.cir | 43 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 43 insertions(+)
 create mode 100644 trunc-1.cir

diff --git a/trunc-1.cir b/trunc-1.cir
new file mode 100644
index 000000000..bde4fc463
--- /dev/null
+++ b/trunc-1.cir
@@ -0,0 +1,43 @@
+* expose time step truncation
+
+v1  1 0  pwl(0s 0 1s 0 2s 1)
+I1  2 0  -1mA
+SW1 2 0  1 0 SWITCH1
+
+* vforce 3 0 pwl(0s 0 1.599s 0 1.600s 1.0)
+
+.MODEL SWITCH1 SW VT=0.5 VH=0.1 RON=1k ROFF=2k
+
+.option method=trap
+
+.control
+
+tran 10ms 4s
+
+let t_gold = 1.6s
+
+let len = length(time)
+let steps = vector(len)
+
+let kk = 0
+repeat $&len
+  let steps[kk] = time[kk] - time[kk ? kk-1 : 0]
+  let kk = kk + 1
+end
+
+
+plot v(1)
+plot v(2)
+
+print  steps  time - t_gold
+plot log(steps)
+
+plot xlimit 1.590 1.610  v(2)
+plot xlimit 1.590 1.610  log(steps)
+
+** the first discharge in more detail:
+*plot v(1) gold xlimit 45.095e-6 45.110e-6
+
+.endc
+
+.end