From 3612ba951c5457c8917d7f965bc237b2d3131a8d Mon Sep 17 00:00:00 2001 From: h_vogt Date: Sat, 18 May 2013 14:57:17 +0200 Subject: [PATCH] indentation --- src/spicelib/analysis/traninit.c | 27 ++++++---------- src/spicelib/devices/bsim4v4/b4v4getic.c | 39 ++++++++++++------------ 2 files changed, 28 insertions(+), 38 deletions(-) diff --git a/src/spicelib/analysis/traninit.c b/src/spicelib/analysis/traninit.c index cfca9426a..b25aa6cf4 100644 --- a/src/spicelib/analysis/traninit.c +++ b/src/spicelib/analysis/traninit.c @@ -21,25 +21,16 @@ int TRANinit(CKTcircuit *ckt, JOB *anal) ckt->CKTstep = job->TRANstep; ckt->CKTinitTime = job->TRANinitTime; ckt->CKTmaxStep = job->TRANmaxStep; - - - - /* The following code has been taken from macspice 3f4 (A. Wilson) - in the file traninit.new.c - Seems interesting */ - if(ckt->CKTmaxStep == 0) - { - if (ckt->CKTstep < ( ckt->CKTfinalTime - ckt->CKTinitTime )/50.0) - { - ckt->CKTmaxStep = ckt->CKTstep; - } - else - { - ckt->CKTmaxStep = ( ckt->CKTfinalTime - ckt->CKTinitTime )/50.0; - } -} - - + /* The following code has been taken from macspice 3f4 (A. Wilson) + in the file traninit.new.c - Seems interesting */ + if(ckt->CKTmaxStep == 0) { + if (ckt->CKTstep < ( ckt->CKTfinalTime - ckt->CKTinitTime )/50.0) + ckt->CKTmaxStep = ckt->CKTstep; + else + ckt->CKTmaxStep = ( ckt->CKTfinalTime - ckt->CKTinitTime )/50.0; + } + ckt->CKTdelmin = 1e-11*ckt->CKTmaxStep; /* XXX */ ckt->CKTmode = job->TRANmode; diff --git a/src/spicelib/devices/bsim4v4/b4v4getic.c b/src/spicelib/devices/bsim4v4/b4v4getic.c index 0b6088dd8..808368e8a 100644 --- a/src/spicelib/devices/bsim4v4/b4v4getic.c +++ b/src/spicelib/devices/bsim4v4/b4v4getic.c @@ -17,28 +17,27 @@ int BSIM4v4getic( -GENmodel *inModel, -CKTcircuit *ckt) + GENmodel *inModel, + CKTcircuit *ckt) { -BSIM4v4model *model = (BSIM4v4model*)inModel; -BSIM4v4instance *here; + BSIM4v4model *model = (BSIM4v4model*)inModel; + BSIM4v4instance *here; - for (; model ; model = model->BSIM4v4nextModel) - { for (here = model->BSIM4v4instances; here; here = here->BSIM4v4nextInstance) - { - if (!here->BSIM4v4icVDSGiven) - { here->BSIM4v4icVDS = *(ckt->CKTrhs + here->BSIM4v4dNode) - - *(ckt->CKTrhs + here->BSIM4v4sNode); - } - if (!here->BSIM4v4icVGSGiven) - { here->BSIM4v4icVGS = *(ckt->CKTrhs + here->BSIM4v4gNodeExt) - - *(ckt->CKTrhs + here->BSIM4v4sNode); - } - if(!here->BSIM4v4icVBSGiven) - { here->BSIM4v4icVBS = *(ckt->CKTrhs + here->BSIM4v4bNode) - - *(ckt->CKTrhs + here->BSIM4v4sNode); - } - } + for (; model ; model = model->BSIM4v4nextModel) { + for (here = model->BSIM4v4instances; here; here = here->BSIM4v4nextInstance) { + if (!here->BSIM4v4icVDSGiven) { + here->BSIM4v4icVDS = *(ckt->CKTrhs + here->BSIM4v4dNode) + - *(ckt->CKTrhs + here->BSIM4v4sNode); + } + if (!here->BSIM4v4icVGSGiven) { + here->BSIM4v4icVGS = *(ckt->CKTrhs + here->BSIM4v4gNodeExt) + - *(ckt->CKTrhs + here->BSIM4v4sNode); + } + if(!here->BSIM4v4icVBSGiven) { + here->BSIM4v4icVBS = *(ckt->CKTrhs + here->BSIM4v4bNode) + - *(ckt->CKTrhs + here->BSIM4v4sNode); + } + } } return(OK); }