From 2e06867da630a151777246fb25ae3a80e9d654e2 Mon Sep 17 00:00:00 2001 From: h_vogt Date: Sun, 21 Nov 2010 15:06:55 +0000 Subject: [PATCH] PULSE: correct timing in case of phase != 0 --- ChangeLog | 4 ++++ src/spicelib/devices/vsrc/vsrcacct.c | 23 ++++++++++++---------- src/spicelib/devices/vsrc/vsrcload.c | 29 ++++++++++++++++------------ 3 files changed, 34 insertions(+), 22 deletions(-) diff --git a/ChangeLog b/ChangeLog index b4621642d..afe6438e5 100644 --- a/ChangeLog +++ b/ChangeLog @@ -1,3 +1,7 @@ +2010-11-21 Holger Vogt + * vsracct.c, vsrcload.c: PULSE: next trial of + correct timing in case of phase != 0 + 2010-11-20 Holger Vogt * vsracct.c: correct timing in case of phase != 0 diff --git a/src/spicelib/devices/vsrc/vsrcacct.c b/src/spicelib/devices/vsrc/vsrcacct.c index 95034cb4c..1270d189b 100644 --- a/src/spicelib/devices/vsrc/vsrcacct.c +++ b/src/spicelib/devices/vsrc/vsrcacct.c @@ -48,7 +48,6 @@ VSRCaccept(CKTcircuit *ckt, GENmodel *inModel) double PHASE; double phase; double deltat; - double basephase; double tshift; #endif double time = 0.; //hvogt @@ -72,20 +71,24 @@ VSRCaccept(CKTcircuit *ckt, GENmodel *inModel) PHASE = here->VSRCfunctionOrder > 7 ? here->VSRCcoeffs[7] : 0.0; #endif - /* offset time by delay and limit to zero */ + /* offset time by delay */ time = ckt->CKTtime - TD; tshift = TD; #ifdef XSPICE - /* normalize phase to 0 - 2PI */ - phase = PHASE * M_PI / 180.0; - basephase = 2 * M_PI * floor(phase / (2 * M_PI)); - phase -= basephase; - - /* compute equivalent delta time and add to time */ - deltat = (phase / (2 * M_PI)) * PER; + /* normalize phase to 0 - 360° */ + /* normalize phase to cycles */ + phase = PHASE / 360.0; + if (phase >=0) + phase -= floor(phase); + else + phase -= ceil(phase); + deltat = phase * PER; + while (deltat > 0) + deltat -= PER; time += deltat; tshift = TD - deltat; - while (tshift < 0) tshift += PER; + while (tshift < 0) + tshift += PER; #endif /* gtri - end - wbk - add PHASE parameter */ diff --git a/src/spicelib/devices/vsrc/vsrcload.c b/src/spicelib/devices/vsrc/vsrcload.c index e0f8e18db..a2c8c6f9d 100644 --- a/src/spicelib/devices/vsrc/vsrcload.c +++ b/src/spicelib/devices/vsrc/vsrcload.c @@ -88,21 +88,26 @@ VSRCload(GENmodel *inModel, CKTcircuit *ckt) && here->VSRCcoeffs[6] != 0.0 ? here->VSRCcoeffs[6] : ckt->CKTfinalTime; #ifdef XSPICE - /* gtri - begin - wbk - add PHASE parameter */ - PHASE = here->VSRCfunctionOrder > 7 - ? here->VSRCcoeffs[7] : 0.0; - - /* normalize phase to 0 - 2PI */ - phase = PHASE * M_PI / 180.0; - basephase = 2 * M_PI * floor(phase / (2 * M_PI)); - phase -= basephase; + /* gtri - begin - wbk - add PHASE parameter */ + PHASE = here->VSRCfunctionOrder > 7 + ? here->VSRCcoeffs[7] : 0.0; - /* compute equivalent delta time and add to time */ - deltat = (phase / (2 * M_PI)) * PER; + /* shift time by delay time TD */ + time = ckt->CKTtime - TD; + + /* normalize phase to cycles */ + phase = PHASE / 360.0; + if (phase >=0) + phase -= floor(phase); + else + phase -= ceil(phase); + deltat = phase * PER; + while (deltat > 0) + deltat -= PER; + /* shift time by pase (neg. for pos. phase value) */ time += deltat; - /* gtri - end - wbk - add PHASE parameter */ + /* gtri - end - wbk - add PHASE parameter */ #endif - time -= TD; if(time > PER) { /* repeating signal - figure out where we are */ /* in period */