From 1a97e1097f5862d6c195c39ccfff3a3cfba2f0f2 Mon Sep 17 00:00:00 2001
From: Giles Atkinson <“gatk555@gmail.com”>
Date: Wed, 26 Apr 2023 21:34:37 +0100
Subject: [PATCH] Fix error in previous fix for Bug #607  -       "DC Source
 with Pulse stops pulsing half way through simulation". Non-periodic PWL
 waveforms reverted to zero on termination.

---
 src/spicelib/devices/vsrc/vsrcload.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/spicelib/devices/vsrc/vsrcload.c b/src/spicelib/devices/vsrc/vsrcload.c
index a4d4f73c6..099daac4f 100644
--- a/src/spicelib/devices/vsrc/vsrcload.c
+++ b/src/spicelib/devices/vsrc/vsrcload.c
@@ -320,6 +320,8 @@ VSRCload(GENmodel *inModel, CKTcircuit *ckt)
                                     here->VSRCcoeffs[here->VSRCrBreakpt];
                                 time -= period * floor(time / period);
                             } else {
+                                value =
+                                    here->VSRCcoeffs[here->VSRCfunctionOrder - 1];
                                 break;
                             }
                         }