From 14fc59b83d8502105339ded60667ec2597ff704c Mon Sep 17 00:00:00 2001
From: dwarning <dwarning>
Date: Tue, 25 Jul 2017 13:46:43 +0200
Subject: [PATCH] bjt, jfet, vbic, dio: allow plotting of small signal
 parameter like charges, capacitances and conductances in dc sweeps

---
 src/spicelib/devices/bjt/bjtload.c   | 2 +-
 src/spicelib/devices/dio/dioload.c   | 2 +-
 src/spicelib/devices/jfet/jfetload.c | 2 +-
 src/spicelib/devices/vbic/vbicload.c | 2 +-
 4 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/spicelib/devices/bjt/bjtload.c b/src/spicelib/devices/bjt/bjtload.c
index bd7bf02c8..82c25d278 100644
--- a/src/spicelib/devices/bjt/bjtload.c
+++ b/src/spicelib/devices/bjt/bjtload.c
@@ -534,7 +534,7 @@ next1:      vtn=vt*here->BJTtemissionCoeffF;
             gmu=gbc/here->BJTtBetaR+gbcn;
             go=(gbc+(cex-cbc)*dqbdvc/qb)/qb;
             gm=(gex-(cex-cbc)*dqbdve/qb)/qb-go;
-            if( (ckt->CKTmode & (MODETRAN | MODEAC)) ||
+            if( (ckt->CKTmode & (MODEDCTRANCURVE | MODETRAN | MODEAC)) ||
                     ((ckt->CKTmode & MODETRANOP) && (ckt->CKTmode & MODEUIC)) ||
                     (ckt->CKTmode & MODEINITSMSIG)) {
                 /*
diff --git a/src/spicelib/devices/dio/dioload.c b/src/spicelib/devices/dio/dioload.c
index aec7df3e6..b39a1b0e6 100644
--- a/src/spicelib/devices/dio/dioload.c
+++ b/src/spicelib/devices/dio/dioload.c
@@ -300,7 +300,7 @@ next1:      if (model->DIOsatSWCurGiven) {              /* sidewall current */
 
             }
 
-            if ((ckt->CKTmode & (MODETRAN | MODEAC | MODEINITSMSIG)) ||
+            if ((ckt->CKTmode & (MODEDCTRANCURVE | MODETRAN | MODEAC | MODEINITSMSIG)) ||
                      ((ckt->CKTmode & MODETRANOP) && (ckt->CKTmode & MODEUIC))) {
               /*
                *   charge storage elements
diff --git a/src/spicelib/devices/jfet/jfetload.c b/src/spicelib/devices/jfet/jfetload.c
index a2c333528..2cf68c326 100644
--- a/src/spicelib/devices/jfet/jfetload.c
+++ b/src/spicelib/devices/jfet/jfetload.c
@@ -400,7 +400,7 @@ JFETload(GENmodel *inModel, CKTcircuit *ckt)
              *   compute equivalent drain current source 
              */
             cd=cdrain-cgd;
-            if ( (ckt->CKTmode & (MODETRAN | MODEAC | MODEINITSMSIG) ) ||
+            if ( (ckt->CKTmode & (MODEDCTRANCURVE | MODETRAN | MODEAC | MODEINITSMSIG) ) ||
                     ((ckt->CKTmode & MODETRANOP) && (ckt->CKTmode & MODEUIC)) ){
                 /* 
                  *    charge storage elements 
diff --git a/src/spicelib/devices/vbic/vbicload.c b/src/spicelib/devices/vbic/vbicload.c
index 0a3f7ee5c..1bf534eb0 100644
--- a/src/spicelib/devices/vbic/vbicload.c
+++ b/src/spicelib/devices/vbic/vbicload.c
@@ -786,7 +786,7 @@ next1:
             Ibcp += ckt->CKTgmin*Vbcp;
             Ibcp_Vbcp += ckt->CKTgmin;
 
-            if( (ckt->CKTmode & (MODETRAN | MODEAC)) ||
+            if( (ckt->CKTmode & (MODEDCTRANCURVE | MODETRAN | MODEAC)) ||
                     ((ckt->CKTmode & MODETRANOP) && (ckt->CKTmode & MODEUIC)) ||
                     (ckt->CKTmode & MODEINITSMSIG)) {
                 /*