From 1203f8f3df6335861281349062dc4f89b8ca422b Mon Sep 17 00:00:00 2001
From: Florian Ballenegger <florian.ballenegger@anamosic.com>
Date: Sat, 12 Sep 2020 15:54:34 +0200
Subject: [PATCH] modified loop example

---
 README.loop            |  1 +
 examples/loop/vreg.cir | 13 +++++++++++--
 2 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/README.loop b/README.loop
index a1085ca72..324978e83 100644
--- a/README.loop
+++ b/README.loop
@@ -55,6 +55,7 @@ Examples
 .loop M2/Gate DEC 10 1 10e9 insrc="Vin" outpos="out" outneg="vcc" dir=-1
 .loop M2 DEC 10 1 10e9 portname="Gate"
 
+A complete example can be found in examples/loop/vreg.cir.
 
 Outputs
 -------
diff --git a/examples/loop/vreg.cir b/examples/loop/vreg.cir
index a5a2df99e..2b895c60b 100644
--- a/examples/loop/vreg.cir
+++ b/examples/loop/vreg.cir
@@ -9,6 +9,7 @@ Mp2 pgate mir vdd vdd p1 W=7.5u L=0.35u pd=13.5u ad=22.5p ps=13.5u as=22.5p m=2
 
 M1 pgate set tail vss n1 W=7.5u L=0.35u pd=13.5u ad=22.5p ps=13.5u as=22.5p m=10
 M2 mir fbinj tail vss n1 W=7.5u L=0.35u pd=13.5u ad=22.5p ps=13.5u as=22.5p m=10
+Cc pgate vdd 10p
 
 Mb1 tail bn vss vss n1 W=7.5u L=0.35u pd=13.5u ad=22.5p ps=13.5u as=22.5p m=4
 Mb0 bn bn vss vss n1 W=7.5u L=0.35u pd=13.5u ad=22.5p ps=13.5u as=22.5p m=4
@@ -20,7 +21,8 @@ Vset set vss DC 1.2 AC 1
 Vvdd vdd vss DC 3.3
 Vvss vss 0 DC 0
 
-Iload out vss DC 10e-3 PWL 1n 10e-3 2n 9e-3
+Cload out vss 100p
+Iload out vss DC 10e-3 PWL 1n 10e-3 2n 1e-3
 
 .model n1 nmos level=49 version=3.3.0 tox=3.5n nch=2.4e17 nsub=5e16 vth0=0.6
 .model p1 pmos level=49 version=3.3.0 tox=3.5n nch=2.5e17 nsub=5e16 vth0=-0.7
@@ -28,4 +30,11 @@ Iload out vss DC 10e-3 PWL 1n 10e-3 2n 9e-3
 
 .loop M2/Gate DEC 10 1 10e9 insrc="Vset" outpos="out" outneg="vss" dir=-1 refnode="set"
 .ac dec 10 1 1e9
-.tran 1n 10u
+.tran 10n 10u
+
+.control
+* quoting names is not necessary inside .control
+loop M2/Gate dec 10 1 10e9 insrc=Vset outsrc=Iload refnode=set dir=-1 name=control
+plot db(T)
+plot db(H) db(Hinf) db(D) db(Dn)
+.endc