From 0c02292c4405ea6aea39cf3e438f876e3d3fdeed Mon Sep 17 00:00:00 2001 From: Francesco Lannutti Date: Fri, 4 Nov 2016 13:40:59 +0100 Subject: [PATCH] Added some examples for Reliability Analysis --- .../Reliability/Carry_chain_1bit_16nm.net | 103 ++ .../Reliability/Carry_chain_1bit_65nm.net | 94 ++ .../Reliability/Carry_chain_32bit_16nm.net | 188 ++++ .../Reliability/Carry_chain_32bit_65nm.net | 187 ++++ examples/Reliability/models/16nm_HP.pm | 142 +++ examples/Reliability/models/65nm_bulk.pm | 147 +++ examples/Reliability/not_relan_65nm.cir | 37 + examples/Reliability/prova_relan.cir | 37 + examples/Reliability/subckt/sottocircuiti | 906 ++++++++++++++++++ 9 files changed, 1841 insertions(+) create mode 100644 examples/Reliability/Carry_chain_1bit_16nm.net create mode 100644 examples/Reliability/Carry_chain_1bit_65nm.net create mode 100644 examples/Reliability/Carry_chain_32bit_16nm.net create mode 100644 examples/Reliability/Carry_chain_32bit_65nm.net create mode 100644 examples/Reliability/models/16nm_HP.pm create mode 100644 examples/Reliability/models/65nm_bulk.pm create mode 100644 examples/Reliability/not_relan_65nm.cir create mode 100644 examples/Reliability/prova_relan.cir create mode 100644 examples/Reliability/subckt/sottocircuiti diff --git a/examples/Reliability/Carry_chain_1bit_16nm.net b/examples/Reliability/Carry_chain_1bit_16nm.net new file mode 100644 index 000000000..30e9aa225 --- /dev/null +++ b/examples/Reliability/Carry_chain_1bit_16nm.net @@ -0,0 +1,103 @@ +carry_chain_1bit_16nm + +.include ./models/16nm_HP.pm +.include ./subckt/sottocircuiti + +.subckt FA_SUB 0 node1 nodeSo nodeCo nodeC nodeB nodeA XX=1 + +Mn1 nodecon nodeb node4 0 nmos W={2*XX*Wmin} L={Lmin} +Mp1 1 nodea node1 node1 pmos W={4*XX*Wmin} L={Lmin} + +Mn2 node4 nodea 0 0 nmos W={2*XX*Wmin} L={Lmin} +Mp2 1 nodeb node1 node1 pmos W={4*XX*Wmin} L={Lmin} + + +Mn3 5 nodea 0 0 nmos W={2*XX*Wmin} L={Lmin} + +Mp3 4 nodea node1 node1 pmos W={4*XX*Wmin} L={Lmin} +Mp4 nodecon nodeb 4 node1 pmos W={4*XX*Wmin} L={Lmin} + +Mn4 5 nodeb 0 0 nmos W={2*XX*Wmin} L={Lmin} + +Mp5 nodecon nodec 1 node1 pmos W={4*XX*Wmin} L={Lmin} +Mn5 nodecon nodec 5 0 nmos W={2*XX*Wmin} L={Lmin} + +Mp6 2 nodea node1 node1 pmos W={4*XX*Wmin} L={Lmin} + +Mn6 3 nodea 0 0 nmos W={2*XX*Wmin} L={Lmin} +Mp7 2 nodeb node1 node1 pmos W={4*XX*Wmin} L={Lmin} + +Mn7 3 nodeb 0 0 nmos W={2*XX*Wmin} L={Lmin} + +Mp8 2 nodec node1 node1 pmos W={4*XX*Wmin} L={Lmin} + +Mn8 3 nodec 0 0 nmos W={2*XX*Wmin} L={Lmin} + +Mp9 nodeson nodecon 2 node1 pmos W={4*XX*Wmin} L={Lmin} + +Mn9 nodeson nodecon 3 0 nmos W={2*XX*Wmin} L={Lmin} + +Mp10 9 nodea node1 node1 pmos W={6*XX*Wmin} L={Lmin} +Mn10 7 nodea 0 0 nmos W={3*XX*Wmin} L={Lmin} +Mp11 8 nodeb 9 node1 pmos W={6*XX*Wmin} L={Lmin} + +Mn11 6 nodeb 7 0 nmos W={3*XX*Wmin} L={Lmin} +Mp12 nodeSon nodec 8 node1 pmos W={6*XX*Wmin} L={Lmin} + +Mn12 nodeSon nodec 6 0 nmos W={3*XX*Wmin} L={Lmin} + +Mp13 nodeCo nodecon node1 node1 pmos W={4*XX*Wmin} L={Lmin} +Mn13 nodeCo nodecon 0 0 nmos W={2*XX*Wmin} L={Lmin} + +Mp14 nodeSo nodeSon node1 node1 pmos W={4*XX*Wmin} L={Lmin} +Mn14 nodeSo nodeSon 0 0 nmos W={2*XX*Wmin} L={Lmin} +.ends + + +.options temp=125 tnom=125 +.model p1_ra relmodel level=1 type=1 +.appendmodel p1_ra pmos +.relan 315360000 0.002ns 1.4ns + +.TRAN 0.002ns 1.4ns + +.PARAM Y=0.78 +.PARAM XX=1 +.PARAM Lmin=16n +.PARAM Wmin=16n + +*.meas tran delay_LH trig v(cin) val='0.9*Y*0.5' rise=1 targ v(cout) val='0.9*Y*0.5' fall=1 +.meas tran delay_HL trig v(cin) val='0.9*Y*0.5' fall=1 targ v(cout) val='0.9*Y*0.5' fall=1 +.meas tran delay_HL_1 trig v(cin) val='0.9*Y*0.5' fall=1 targ v(xfa_1.nodecon) val='0.9*Y*0.5' rise=1 +.meas tran delay_HL_2 trig v(xfa_1.nodecon) val='0.9*Y*0.5' rise=1 targ v(cout) val='0.9*Y*0.5' fall=1 + +*.meas tran delay_LH_c trig v(cin) val={0.45*Y} rise=1 targ v(1) val={0.45*Y} rise=1 +*.meas tran delay_HL_c trig v(cin) val={0.45*Y} fall=1 targ v(1) val={0.45*Y} fall=1 +*.meas tran delay_HL_s trig v(cin) val={0.45*Y} rise=1 targ v(out1) val={0.45*Y} fall=1 +*.meas tran delay_LH_s trig v(cin) val={0.45*Y} fall=1 targ v(out1) val={0.45*Y} rise=1 + +Vdd VDD 0 {0.9*Y} + +Vina1 ina1 0 0 + +Vinb1 inb1 0 {0.9*Y} + + +* Francesco +*vcin cin 0 PWL(0 0 0.100ns 0 0.120ns {0.9*Y}) +vcin cin 0 PWL(0 {0.9*Y} 0.100ns {0.9*Y} 0.120ns 0) + + +*vcin cin 0 PWL(0 {0.9*Y} 0.100ns {0.9*Y} 0.120ns 0) +*vcin cin 0 PWL(0 0 0.100ns 0 0.120ns {0.9*Y}) + +XFA_1 0 VDD out cout cin inb1 ina1 FA_SUB + +xNOT4_1 0 VDD out1 out NOT4_SUB +xNOT4_2 0 VDD cout1 cout NOT4_SUB + +.CONTROL +run +.ENDC + +.END diff --git a/examples/Reliability/Carry_chain_1bit_65nm.net b/examples/Reliability/Carry_chain_1bit_65nm.net new file mode 100644 index 000000000..b4dd3634d --- /dev/null +++ b/examples/Reliability/Carry_chain_1bit_65nm.net @@ -0,0 +1,94 @@ +carry_chain_1bit_65nm + +.include ./models/65nm_bulk.pm +.include ./subckt/sottocircuiti + +.subckt FA_SUB 0 node1 nodeSo nodeCo nodeC nodeB nodeA XX=1 + +Mn1 nodecon nodeb node4 0 nmos W={2*XX*Wmin} L={Lmin} +Mp1 1 nodea node1 node1 pmos W={4*XX*Wmin} L={Lmin} + +Mn2 node4 nodea 0 0 nmos W={2*XX*Wmin} L={Lmin} +Mp2 1 nodeb node1 node1 pmos W={4*XX*Wmin} L={Lmin} + +Mn3 5 nodea 0 0 nmos W={2*XX*Wmin} L={Lmin} + +Mp3 4 nodea node1 node1 pmos W={4*XX*Wmin} L={Lmin} +Mp4 nodecon nodeb 4 node1 pmos W={4*XX*Wmin} L={Lmin} + +Mn4 5 nodeb 0 0 nmos W={2*XX*Wmin} L={Lmin} + +Mp5 nodecon nodec 1 node1 pmos W={4*XX*Wmin} L={Lmin} +Mn5 nodecon nodec 5 0 nmos W={2*XX*Wmin} L={Lmin} + +Mp6 2 nodea node1 node1 pmos W={4*XX*Wmin} L={Lmin} + +Mn6 3 nodea 0 0 nmos W={2*XX*Wmin} L={Lmin} +Mp7 2 nodeb node1 node1 pmos W={4*XX*Wmin} L={Lmin} + +Mn7 3 nodeb 0 0 nmos W={2*XX*Wmin} L={Lmin} + +Mp8 2 nodec node1 node1 pmos W={4*XX*Wmin} L={Lmin} + +Mn8 3 nodec 0 0 nmos W={2*XX*Wmin} L={Lmin} + +Mp9 nodeson nodecon 2 node1 pmos W={4*XX*Wmin} L={Lmin} + +Mn9 nodeson nodecon 3 0 nmos W={2*XX*Wmin} L={Lmin} + +Mp10 9 nodea node1 node1 pmos W={6*XX*Wmin} L={Lmin} +Mn10 7 nodea 0 0 nmos W={3*XX*Wmin} L={Lmin} +Mp11 8 nodeb 9 node1 pmos W={6*XX*Wmin} L={Lmin} + +Mn11 6 nodeb 7 0 nmos W={3*XX*Wmin} L={Lmin} +Mp12 nodeSon nodec 8 node1 pmos W={6*XX*Wmin} L={Lmin} + +Mn12 nodeSon nodec 6 0 nmos W={3*XX*Wmin} L={Lmin} + +Mp13 nodeCo nodecon node1 node1 pmos W={4*XX*Wmin} L={Lmin} +Mn13 nodeCo nodecon 0 0 nmos W={2*XX*Wmin} L={Lmin} + +Mp14 nodeSo nodeSon node1 node1 pmos W={4*XX*Wmin} L={Lmin} +Mn14 nodeSo nodeSon 0 0 nmos W={2*XX*Wmin} L={Lmin} +.ends + +*.options temp=125 tnom=125 + +.model p1_ra relmodel level=1 type=2 +.appendmodel p1_ra pmos +.relan 315360000 0.002ns 1.4ns + +.TRAN 0.002ns 1.4ns + +.PARAM Y=1.33 +.PARAM XX=1 +.PARAM Lmin=65n +.PARAM Wmin=65n + +*.meas tran delay_LH trig v(cin) val='0.9*Y*0.5' rise=1 targ v(cout) val='0.9*Y*0.5' fall=1 +.meas tran delay_HL trig v(cin) val='0.9*Y*0.5' fall=1 targ v(cout) val='0.9*Y*0.5' fall=1 +.meas tran delay_HL_1 trig v(cin) val='0.9*Y*0.5' fall=1 targ v(xfa_1.nodecon) val='0.9*Y*0.5' rise=1 +.meas tran delay_HL_2 trig v(xfa_1.nodecon) val='0.9*Y*0.5' rise=1 targ v(cout) val='0.9*Y*0.5' fall=1 + +Vdd VDD 0 {0.9*Y} + +Vina1 ina1 0 0 + +Vinb1 inb1 0 {0.9*Y} + + +* Francesco +*vcin cin 0 PWL(0 0 0.100ns 0 0.120ns {0.9*Y}) +vcin cin 0 PWL(0 {0.9*Y} 0.100ns {0.9*Y} 0.120ns 0) + + +XFA_1 0 VDD out cout cin inb1 ina1 FA_SUB + +xNOT4_1 0 VDD out1 out NOT4_SUB +xNOT4_2 0 VDD cout1 cout NOT4_SUB + +.CONTROL + run +.ENDC + +.END diff --git a/examples/Reliability/Carry_chain_32bit_16nm.net b/examples/Reliability/Carry_chain_32bit_16nm.net new file mode 100644 index 000000000..482bd1dbe --- /dev/null +++ b/examples/Reliability/Carry_chain_32bit_16nm.net @@ -0,0 +1,188 @@ +carry_chain_32bit_16nm + +.include ./models/16nm_HP.pm + +.subckt NOT4_SUB 1 2 3 4 XX=4 +Mn1 3 4 1 1 nmos W={1*XX*Wmin} L={Lmin} +Mp1 3 4 2 2 pmos W={2*XX*Wmin} L={Lmin} +.ends + +.subckt FA_SUB 0 node1 nodeSo nodeCo nodeC nodeB nodeA XX=1 + +Mn1 nodecon nodeb node4 0 nmos W={2*XX*Wmin} L={Lmin} +Mp1 1 nodea node1 node1 pmos W={4*XX*Wmin} L={Lmin} + +Mn2 node4 nodea 0 0 nmos W={2*XX*Wmin} L={Lmin} +Mp2 1 nodeb node1 node1 pmos W={4*XX*Wmin} L={Lmin} + + +Mn3 5 nodea 0 0 nmos W={2*XX*Wmin} L={Lmin} + +Mp3 4 nodea node1 node1 pmos W={4*XX*Wmin} L={Lmin} +Mp4 nodecon nodeb 4 node1 pmos W={4*XX*Wmin} L={Lmin} + +Mn4 5 nodeb 0 0 nmos W={2*XX*Wmin} L={Lmin} + +Mp5 nodecon nodec 1 node1 pmos W={4*XX*Wmin} L={Lmin} +Mn5 nodecon nodec 5 0 nmos W={2*XX*Wmin} L={Lmin} + +Mp6 2 nodea node1 node1 pmos W={4*XX*Wmin} L={Lmin} + +Mn6 3 nodea 0 0 nmos W={2*XX*Wmin} L={Lmin} +Mp7 2 nodeb node1 node1 pmos W={4*XX*Wmin} L={Lmin} + +Mn7 3 nodeb 0 0 nmos W={2*XX*Wmin} L={Lmin} + +Mp8 2 nodec node1 node1 pmos W={4*XX*Wmin} L={Lmin} + +Mn8 3 nodec 0 0 nmos W={2*XX*Wmin} L={Lmin} + +Mp9 nodeson nodecon 2 node1 pmos W={4*XX*Wmin} L={Lmin} + +Mn9 nodeson nodecon 3 0 nmos W={2*XX*Wmin} L={Lmin} + +Mp10 9 nodea node1 node1 pmos W={6*XX*Wmin} L={Lmin} +Mn10 7 nodea 0 0 nmos W={3*XX*Wmin} L={Lmin} +Mp11 8 nodeb 9 node1 pmos W={6*XX*Wmin} L={Lmin} + +Mn11 6 nodeb 7 0 nmos W={3*XX*Wmin} L={Lmin} +Mp12 nodeSon nodec 8 node1 pmos W={6*XX*Wmin} L={Lmin} + +Mn12 nodeSon nodec 6 0 nmos W={3*XX*Wmin} L={Lmin} + +Mp13 nodeCo nodecon node1 node1 pmos W={4*XX*Wmin} L={Lmin} +Mn13 nodeCo nodecon 0 0 nmos W={2*XX*Wmin} L={Lmin} + +Mp14 nodeSo nodeSon node1 node1 pmos W={4*XX*Wmin} L={Lmin} +Mn14 nodeSo nodeSon 0 0 nmos W={2*XX*Wmin} L={Lmin} +.ends + + +.model p1_ra relmodel level=1 type=1 +.appendmodel p1_ra pmos +.relan 315360000 0.002ns 1.4ns + +.TRAN 0.002ns 1.4ns + +.PARAM Y=0.78 +.PARAM XX=1 +.PARAM Lmin=16n +.PARAM Wmin=16n + +.meas tran delay_LH trig v(cin) val='0.9*Y*0.5' rise=1 targ v(cout32) val='0.9*Y*0.5' rise=1 +*.meas tran delay_HL trig v(cin) val='0.9*Y*0.5' fall=1 targ v(cout32) val='0.9*Y*0.5' fall=1 + + +Vdd VDD 0 {0.9*Y} + +Vina1 ina1 0 0 +Vina2 ina2 0 0 +Vina3 ina3 0 0 +Vina4 ina4 0 0 +Vina5 ina5 0 0 +Vina6 ina6 0 0 +Vina7 ina7 0 0 +Vina8 ina8 0 0 +Vina9 ina9 0 0 +Vina10 ina10 0 0 +Vina11 ina11 0 0 +Vina12 ina12 0 0 +Vina13 ina13 0 0 +Vina14 ina14 0 0 +Vina15 ina15 0 0 +Vina16 ina16 0 0 +Vina17 ina17 0 0 +Vina18 ina18 0 0 +Vina19 ina19 0 0 +Vina20 ina20 0 0 +Vina21 ina21 0 0 +Vina22 ina22 0 0 +Vina23 ina23 0 0 +Vina24 ina24 0 0 +Vina25 ina25 0 0 +Vina26 ina26 0 0 +Vina27 ina27 0 0 +Vina28 ina28 0 0 +Vina29 ina29 0 0 +Vina30 ina30 0 0 +Vina31 ina31 0 0 +Vina32 ina32 0 0 + +Vinb1 inb1 0 {0.9*Y} +Vinb2 inb2 0 {0.9*Y} +Vinb3 inb3 0 {0.9*Y} +Vinb4 inb4 0 {0.9*Y} +Vinb5 inb5 0 {0.9*Y} +Vinb6 inb6 0 {0.9*Y} +Vinb7 inb7 0 {0.9*Y} +Vinb8 inb8 0 {0.9*Y} +Vinb9 inb9 0 {0.9*Y} +Vinb10 inb10 0 {0.9*Y} +Vinb11 inb11 0 {0.9*Y} +Vinb12 inb12 0 {0.9*Y} +Vinb13 inb13 0 {0.9*Y} +Vinb14 inb14 0 {0.9*Y} +Vinb15 inb15 0 {0.9*Y} +Vinb16 inb16 0 {0.9*Y} +Vinb17 inb17 0 {0.9*Y} +Vinb18 inb18 0 {0.9*Y} +Vinb19 inb19 0 {0.9*Y} +Vinb20 inb20 0 {0.9*Y} +Vinb21 inb21 0 {0.9*Y} +Vinb22 inb22 0 {0.9*Y} +Vinb23 inb23 0 {0.9*Y} +Vinb24 inb24 0 {0.9*Y} +Vinb25 inb25 0 {0.9*Y} +Vinb26 inb26 0 {0.9*Y} +Vinb27 inb27 0 {0.9*Y} +Vinb28 inb28 0 {0.9*Y} +Vinb29 inb29 0 {0.9*Y} +Vinb30 inb30 0 {0.9*Y} +Vinb31 inb31 0 {0.9*Y} +Vinb32 inb32 0 {0.9*Y} + +vcin cin 0 PWL(0 0 0.100ns 0 0.120ns {0.9*Y}) +*vcin cin 0 PWL(0 {0.9*Y} 0.100ns {0.9*Y} 0.120ns 0) +*vcin cin 0 PWL(0 0 0.100ns 0 0.120ns 0.9 0.240ns 0.9 0.960ns 0 1ns 0 1.02n 0.9 2n 0.9 ) + +XFA_1 0 VDD out1 cout1 cin inb1 ina1 FA_SUB +XFA_2 0 VDD out2 cout2 cout1 inb2 ina2 FA_SUB +XFA_3 0 VDD out3 cout3 cout2 inb3 ina3 FA_SUB +XFA_4 0 VDD out4 cout4 cout3 inb4 ina4 FA_SUB +XFA_5 0 VDD out5 cout5 cout4 inb5 ina5 FA_SUB +XFA_6 0 VDD out6 cout6 cout5 inb6 ina6 FA_SUB +XFA_7 0 VDD out7 cout7 cout6 inb7 ina7 FA_SUB +XFA_8 0 VDD out8 cout8 cout7 inb8 ina8 FA_SUB +XFA_9 0 VDD out9 cout9 cout8 inb9 ina9 FA_SUB +XFA_10 0 VDD out10 cout10 cout9 inb10 ina10 FA_SUB +XFA_11 0 VDD out11 cout11 cout10 inb11 ina11 FA_SUB +XFA_12 0 VDD out12 cout12 cout11 inb12 ina12 FA_SUB +XFA_13 0 VDD out13 cout13 cout12 inb13 ina13 FA_SUB +XFA_14 0 VDD out14 cout14 cout13 inb14 ina14 FA_SUB +XFA_15 0 VDD out15 cout15 cout14 inb15 ina15 FA_SUB +XFA_16 0 VDD out16 cout16 cout15 inb16 ina16 FA_SUB +XFA_17 0 VDD out17 cout17 cout16 inb17 ina17 FA_SUB +XFA_18 0 VDD out18 cout18 cout17 inb18 ina18 FA_SUB +XFA_19 0 VDD out19 cout19 cout18 inb19 ina19 FA_SUB +XFA_20 0 VDD out20 cout20 cout19 inb20 ina20 FA_SUB +XFA_21 0 VDD out21 cout21 cout20 inb21 ina21 FA_SUB +XFA_22 0 VDD out22 cout22 cout21 inb22 ina22 FA_SUB +XFA_23 0 VDD out23 cout23 cout22 inb23 ina23 FA_SUB +XFA_24 0 VDD out24 cout24 cout23 inb24 ina24 FA_SUB +XFA_25 0 VDD out25 cout25 cout24 inb25 ina25 FA_SUB +XFA_26 0 VDD out26 cout26 cout25 inb26 ina26 FA_SUB +XFA_27 0 VDD out27 cout27 cout26 inb27 ina27 FA_SUB +XFA_28 0 VDD out28 cout28 cout27 inb28 ina28 FA_SUB +XFA_29 0 VDD out29 cout29 cout28 inb29 ina29 FA_SUB +XFA_30 0 VDD out30 cout30 cout29 inb30 ina30 FA_SUB +XFA_31 0 VDD out31 cout31 cout30 inb31 ina31 FA_SUB +XFA_32 0 VDD out32 cout32 cout31 inb32 ina32 FA_SUB + +xNOT4_1 0 VDD out_load out32 NOT4_SUB +xNOT4_2 0 VDD cout_load cout32 NOT4_SUB + +.CONTROL +run +.ENDC + +.END diff --git a/examples/Reliability/Carry_chain_32bit_65nm.net b/examples/Reliability/Carry_chain_32bit_65nm.net new file mode 100644 index 000000000..572321ba1 --- /dev/null +++ b/examples/Reliability/Carry_chain_32bit_65nm.net @@ -0,0 +1,187 @@ +carry_chain_32bit_65nm + +.include ./models/65nm_bulk.pm + +.subckt NOT4_SUB 1 2 3 4 XX=4 +Mn1 3 4 1 1 nmos W={1*XX*Wmin} L={Lmin} +Mp1 3 4 2 2 pmos W={2*XX*Wmin} L={Lmin} +.ends + +.subckt FA_SUB 0 node1 nodeSo nodeCo nodeC nodeB nodeA XX=1 + +Mn1 nodecon nodeb node4 0 nmos W={2*XX*Wmin} L={Lmin} +Mp1 1 nodea node1 node1 pmos W={4*XX*Wmin} L={Lmin} + +Mn2 node4 nodea 0 0 nmos W={2*XX*Wmin} L={Lmin} +Mp2 1 nodeb node1 node1 pmos W={4*XX*Wmin} L={Lmin} + +Mn3 5 nodea 0 0 nmos W={2*XX*Wmin} L={Lmin} + +Mp3 4 nodea node1 node1 pmos W={4*XX*Wmin} L={Lmin} +Mp4 nodecon nodeb 4 node1 pmos W={4*XX*Wmin} L={Lmin} + +Mn4 5 nodeb 0 0 nmos W={2*XX*Wmin} L={Lmin} + +Mp5 nodecon nodec 1 node1 pmos W={4*XX*Wmin} L={Lmin} +Mn5 nodecon nodec 5 0 nmos W={2*XX*Wmin} L={Lmin} + +Mp6 2 nodea node1 node1 pmos W={4*XX*Wmin} L={Lmin} + +Mn6 3 nodea 0 0 nmos W={2*XX*Wmin} L={Lmin} +Mp7 2 nodeb node1 node1 pmos W={4*XX*Wmin} L={Lmin} + +Mn7 3 nodeb 0 0 nmos W={2*XX*Wmin} L={Lmin} + +Mp8 2 nodec node1 node1 pmos W={4*XX*Wmin} L={Lmin} + +Mn8 3 nodec 0 0 nmos W={2*XX*Wmin} L={Lmin} + +Mp9 nodeson nodecon 2 node1 pmos W={4*XX*Wmin} L={Lmin} + +Mn9 nodeson nodecon 3 0 nmos W={2*XX*Wmin} L={Lmin} + +Mp10 9 nodea node1 node1 pmos W={6*XX*Wmin} L={Lmin} +Mn10 7 nodea 0 0 nmos W={3*XX*Wmin} L={Lmin} +Mp11 8 nodeb 9 node1 pmos W={6*XX*Wmin} L={Lmin} + +Mn11 6 nodeb 7 0 nmos W={3*XX*Wmin} L={Lmin} +Mp12 nodeSon nodec 8 node1 pmos W={6*XX*Wmin} L={Lmin} + +Mn12 nodeSon nodec 6 0 nmos W={3*XX*Wmin} L={Lmin} + +Mp13 nodeCo nodecon node1 node1 pmos W={4*XX*Wmin} L={Lmin} +Mn13 nodeCo nodecon 0 0 nmos W={2*XX*Wmin} L={Lmin} + +Mp14 nodeSo nodeSon node1 node1 pmos W={4*XX*Wmin} L={Lmin} +Mn14 nodeSo nodeSon 0 0 nmos W={2*XX*Wmin} L={Lmin} +.ends + + +.model p1_ra relmodel level=1 type=2 +.appendmodel p1_ra pmos +.relan 315360000 4ps 4ns + +.TRAN 4ps 4ns + +.PARAM Y=1.33 +.PARAM XX=1 +.PARAM Lmin=65n +.PARAM Wmin=65n + +*.meas tran delay_LH trig v(cin) val='0.9*Y*0.5' rise=1 targ v(cout32) val='0.9*Y*0.5' rise=1 +.meas tran delay_HL trig v(cin) val='0.9*Y*0.5' fall=1 targ v(cout32) val='0.9*Y*0.5' fall=1 + + +Vdd VDD 0 {0.9*Y} + +Vina1 ina1 0 0 +Vina2 ina2 0 0 +Vina3 ina3 0 0 +Vina4 ina4 0 0 +Vina5 ina5 0 0 +Vina6 ina6 0 0 +Vina7 ina7 0 0 +Vina8 ina8 0 0 +Vina9 ina9 0 0 +Vina10 ina10 0 0 +Vina11 ina11 0 0 +Vina12 ina12 0 0 +Vina13 ina13 0 0 +Vina14 ina14 0 0 +Vina15 ina15 0 0 +Vina16 ina16 0 0 +Vina17 ina17 0 0 +Vina18 ina18 0 0 +Vina19 ina19 0 0 +Vina20 ina20 0 0 +Vina21 ina21 0 0 +Vina22 ina22 0 0 +Vina23 ina23 0 0 +Vina24 ina24 0 0 +Vina25 ina25 0 0 +Vina26 ina26 0 0 +Vina27 ina27 0 0 +Vina28 ina28 0 0 +Vina29 ina29 0 0 +Vina30 ina30 0 0 +Vina31 ina31 0 0 +Vina32 ina32 0 0 + +Vinb1 inb1 0 {0.9*Y} +Vinb2 inb2 0 {0.9*Y} +Vinb3 inb3 0 {0.9*Y} +Vinb4 inb4 0 {0.9*Y} +Vinb5 inb5 0 {0.9*Y} +Vinb6 inb6 0 {0.9*Y} +Vinb7 inb7 0 {0.9*Y} +Vinb8 inb8 0 {0.9*Y} +Vinb9 inb9 0 {0.9*Y} +Vinb10 inb10 0 {0.9*Y} +Vinb11 inb11 0 {0.9*Y} +Vinb12 inb12 0 {0.9*Y} +Vinb13 inb13 0 {0.9*Y} +Vinb14 inb14 0 {0.9*Y} +Vinb15 inb15 0 {0.9*Y} +Vinb16 inb16 0 {0.9*Y} +Vinb17 inb17 0 {0.9*Y} +Vinb18 inb18 0 {0.9*Y} +Vinb19 inb19 0 {0.9*Y} +Vinb20 inb20 0 {0.9*Y} +Vinb21 inb21 0 {0.9*Y} +Vinb22 inb22 0 {0.9*Y} +Vinb23 inb23 0 {0.9*Y} +Vinb24 inb24 0 {0.9*Y} +Vinb25 inb25 0 {0.9*Y} +Vinb26 inb26 0 {0.9*Y} +Vinb27 inb27 0 {0.9*Y} +Vinb28 inb28 0 {0.9*Y} +Vinb29 inb29 0 {0.9*Y} +Vinb30 inb30 0 {0.9*Y} +Vinb31 inb31 0 {0.9*Y} +Vinb32 inb32 0 {0.9*Y} + +*vcin cin 0 PWL(0 0 0.100ns 0 0.120ns {0.9*Y}) +*vcin cin 0 PWL(0 {0.9*Y} 0.100ns {0.9*Y} 0.120ns 0) +vcin cin 0 PWL(0 {0.9*Y} 0.100ns {0.9*Y} 0.120ns 0 1.120ns 0 1.140ns {0.9*Y} 2.140ns {0.9*Y} 2.160ns 0) + +XFA_1 0 VDD out1 cout1 cin inb1 ina1 FA_SUB +XFA_2 0 VDD out2 cout2 cout1 inb2 ina2 FA_SUB +XFA_3 0 VDD out3 cout3 cout2 inb3 ina3 FA_SUB +XFA_4 0 VDD out4 cout4 cout3 inb4 ina4 FA_SUB +XFA_5 0 VDD out5 cout5 cout4 inb5 ina5 FA_SUB +XFA_6 0 VDD out6 cout6 cout5 inb6 ina6 FA_SUB +XFA_7 0 VDD out7 cout7 cout6 inb7 ina7 FA_SUB +XFA_8 0 VDD out8 cout8 cout7 inb8 ina8 FA_SUB +XFA_9 0 VDD out9 cout9 cout8 inb9 ina9 FA_SUB +XFA_10 0 VDD out10 cout10 cout9 inb10 ina10 FA_SUB +XFA_11 0 VDD out11 cout11 cout10 inb11 ina11 FA_SUB +XFA_12 0 VDD out12 cout12 cout11 inb12 ina12 FA_SUB +XFA_13 0 VDD out13 cout13 cout12 inb13 ina13 FA_SUB +XFA_14 0 VDD out14 cout14 cout13 inb14 ina14 FA_SUB +XFA_15 0 VDD out15 cout15 cout14 inb15 ina15 FA_SUB +XFA_16 0 VDD out16 cout16 cout15 inb16 ina16 FA_SUB +XFA_17 0 VDD out17 cout17 cout16 inb17 ina17 FA_SUB +XFA_18 0 VDD out18 cout18 cout17 inb18 ina18 FA_SUB +XFA_19 0 VDD out19 cout19 cout18 inb19 ina19 FA_SUB +XFA_20 0 VDD out20 cout20 cout19 inb20 ina20 FA_SUB +XFA_21 0 VDD out21 cout21 cout20 inb21 ina21 FA_SUB +XFA_22 0 VDD out22 cout22 cout21 inb22 ina22 FA_SUB +XFA_23 0 VDD out23 cout23 cout22 inb23 ina23 FA_SUB +XFA_24 0 VDD out24 cout24 cout23 inb24 ina24 FA_SUB +XFA_25 0 VDD out25 cout25 cout24 inb25 ina25 FA_SUB +XFA_26 0 VDD out26 cout26 cout25 inb26 ina26 FA_SUB +XFA_27 0 VDD out27 cout27 cout26 inb27 ina27 FA_SUB +XFA_28 0 VDD out28 cout28 cout27 inb28 ina28 FA_SUB +XFA_29 0 VDD out29 cout29 cout28 inb29 ina29 FA_SUB +XFA_30 0 VDD out30 cout30 cout29 inb30 ina30 FA_SUB +XFA_31 0 VDD out31 cout31 cout30 inb31 ina31 FA_SUB +XFA_32 0 VDD out32 cout32 cout31 inb32 ina32 FA_SUB + +xNOT4_1 0 VDD out_load out32 NOT4_SUB +xNOT4_2 0 VDD cout_load cout32 NOT4_SUB + +.CONTROL +run +.ENDC + +.END diff --git a/examples/Reliability/models/16nm_HP.pm b/examples/Reliability/models/16nm_HP.pm new file mode 100644 index 000000000..effbedd5f --- /dev/null +++ b/examples/Reliability/models/16nm_HP.pm @@ -0,0 +1,142 @@ +* PTM High Performance 16nm Metal Gate / High-K / Strained-Si +* nominal Vdd = 0.7V + +.model nmos nmos level = 54 + ++version = 4.8.0 binunit = 1 paramchk= 1 mobmod = 0 ++capmod = 2 igcmod = 1 igbmod = 1 geomod = 1 ++diomod = 1 rdsmod = 0 rbodymod= 1 rgatemod= 1 ++permod = 1 acnqsmod= 0 trnqsmod= 0 + ++tnom = 27 toxe = 9.5e-010 toxp = 7e-010 toxm = 9.5e-010 ++dtox = 2.5e-010 epsrox = 3.9 wint = 5e-009 lint = 1.45e-009 ++ll = 0 wl = 0 lln = 1 wln = 1 ++lw = 0 ww = 0 lwn = 1 wwn = 1 ++lwl = 0 wwl = 0 xpart = 0 toxref = 9.5e-010 ++xl = -6.5e-9 + ++vth0 = 0.47965 k1 = 0.4 k2 = 0 k3 = 0 ++k3b = 0 w0 = 2.5e-006 dvt0 = 1 dvt1 = 2 ++dvt2 = 0 dvt0w = 0 dvt1w = 0 dvt2w = 0 ++dsub = 0.1 minv = 0.05 voffl = 0 dvtp0 = 1e-011 ++dvtp1 = 0.1 lpe0 = 0 lpeb = 0 xj = 5e-009 ++ngate = 1e+023 ndep = 7e+018 nsd = 2e+020 phin = 0 ++cdsc = 0 cdscb = 0 cdscd = 0 cit = 0 ++voff = -0.13 nfactor = 2.3 eta0 = 0.0032 etab = 0 ++vfb = -0.55 u0 = 0.03 ua = 6e-010 ub = 1.2e-018 ++uc = 0 vsat = 290000 a0 = 1 ags = 0 ++a1 = 0 a2 = 1 b0 = 0 b1 = 0 ++keta = 0.04 dwg = 0 dwb = 0 pclm = 0.02 ++pdiblc1 = 0.001 pdiblc2 = 0.001 pdiblcb = -0.005 drout = 0.5 ++pvag = 1e-020 delta = 0.01 pscbe1 = 8.14e+008 pscbe2 = 1e-007 ++fprout = 0.2 pdits = 0.01 pditsd = 0.23 pditsl = 2300000 ++rsh = 5 rdsw = 140 rsw = 75 rdw = 75 ++rdswmin = 0 rdwmin = 0 rswmin = 0 prwg = 0 ++prwb = 0 wr = 1 alpha0 = 0.074 alpha1 = 0.005 ++beta0 = 30 agidl = 0.0002 bgidl = 2.1e+009 cgidl = 0.0002 ++egidl = 0.8 aigbacc = 0.012 bigbacc = 0.0028 cigbacc = 0.002 ++nigbacc = 1 aigbinv = 0.014 bigbinv = 0.004 cigbinv = 0.004 ++eigbinv = 1.1 nigbinv = 3 aigc = 0.0213 bigc = 0.0025889 ++cigc = 0.002 aigsd = 0.0213 bigsd = 0.0025889 cigsd = 0.002 ++nigc = 1 poxedge = 1 pigcd = 1 ntox = 1 ++xrcrg1 = 12 xrcrg2 = 5 + ++cgso = 5e-011 cgdo = 5e-011 cgbo = 2.56e-011 cgdl = 2.653e-010 ++cgsl = 2.653e-010 ckappas = 0.03 ckappad = 0.03 acde = 1 ++moin = 15 noff = 0.9 voffcv = 0.02 + ++kt1 = -0.11 kt1l = 0 kt2 = 0.022 ute = -1.5 ++ua1 = 4.31e-009 ub1 = 7.61e-018 uc1 = -5.6e-011 prt = 0 ++at = 33000 + ++fnoimod = 1 tnoimod = 0 + ++jss = 0.0001 jsws = 1e-011 jswgs = 1e-010 njs = 1 ++ijthsfwd= 0.01 ijthsrev= 0.001 bvs = 10 xjbvs = 1 ++jsd = 0.0001 jswd = 1e-011 jswgd = 1e-010 njd = 1 ++ijthdfwd= 0.01 ijthdrev= 0.001 bvd = 10 xjbvd = 1 ++pbs = 1 cjs = 0.0005 mjs = 0.5 pbsws = 1 ++cjsws = 5e-010 mjsws = 0.33 pbswgs = 1 cjswgs = 3e-010 ++mjswgs = 0.33 pbd = 1 cjd = 0.0005 mjd = 0.5 ++pbswd = 1 cjswd = 5e-010 mjswd = 0.33 pbswgd = 1 ++cjswgd = 5e-010 mjswgd = 0.33 tpb = 0.005 tcj = 0.001 ++tpbsw = 0.005 tcjsw = 0.001 tpbswg = 0.005 tcjswg = 0.001 ++xtis = 3 xtid = 3 + ++dmcg = 0 dmci = 0 dmdg = 0 dmcgt = 0 ++dwj = 0 xgw = 0 xgl = 0 + ++rshg = 0.4 gbmin = 1e-010 rbpb = 5 rbpd = 15 ++rbps = 15 rbdb = 15 rbsb = 15 ngcon = 1 + + +.model pmos pmos level = 54 + ++version = 4.8.0 binunit = 1 paramchk= 1 mobmod = 0 ++capmod = 2 igcmod = 1 igbmod = 1 geomod = 1 ++diomod = 1 rdsmod = 0 rbodymod= 1 rgatemod= 1 ++permod = 1 acnqsmod= 0 trnqsmod= 0 + ++tnom = 27 toxe = 1e-009 toxp = 7e-010 toxm = 1e-009 ++dtox = 3e-010 epsrox = 3.9 wint = 5e-009 lint = 1.45e-009 ++ll = 0 wl = 0 lln = 1 wln = 1 ++lw = 0 ww = 0 lwn = 1 wwn = 1 ++lwl = 0 wwl = 0 xpart = 0 toxref = 1e-009 ++xl = -6.5e-9 + ++vth0 = -0.43121 k1 = 0.4 k2 = -0.01 k3 = 0 ++k3b = 0 w0 = 2.5e-006 dvt0 = 1 dvt1 = 2 ++dvt2 = -0.032 dvt0w = 0 dvt1w = 0 dvt2w = 0 ++dsub = 0.1 minv = 0.05 voffl = 0 dvtp0 = 1e-011 ++dvtp1 = 0.05 lpe0 = 0 lpeb = 0 xj = 5e-009 ++ngate = 1e+023 ndep = 5.5e+018 nsd = 2e+020 phin = 0 ++cdsc = 0 cdscb = 0 cdscd = 0 cit = 0 ++voff = -0.126 nfactor = 2.1 eta0 = 0.0032 etab = 0 ++vfb = 0.55 u0 = 0.006 ua = 2e-009 ub = 5e-019 ++uc = 0 vsat = 250000 a0 = 1 ags = 1e-020 ++a1 = 0 a2 = 1 b0 = 0 b1 = 0 ++keta = -0.047 dwg = 0 dwb = 0 pclm = 0.12 ++pdiblc1 = 0.001 pdiblc2 = 0.001 pdiblcb = 3.4e-008 drout = 0.56 ++pvag = 1e-020 delta = 0.01 pscbe1 = 1.2e+009 pscbe2 = 8.0472e-007 ++fprout = 0.2 pdits = 0.08 pditsd = 0.23 pditsl = 2300000 ++rsh = 5 rdsw = 140 rsw = 70 rdw = 70 ++rdswmin = 0 rdwmin = 0 rswmin = 0 prwg = 0 ++prwb = 0 wr = 1 alpha0 = 0.074 alpha1 = 0.005 ++beta0 = 30 agidl = 0.0002 bgidl = 2.1e+009 cgidl = 0.0002 ++egidl = 0.8 aigbacc = 0.012 bigbacc = 0.0028 cigbacc = 0.002 ++nigbacc = 1 aigbinv = 0.014 bigbinv = 0.004 cigbinv = 0.004 ++eigbinv = 1.1 nigbinv = 3 aigc = 0.0213 bigc = 0.0025889 ++cigc = 0.002 aigsd = 0.0213 bigsd = 0.0025889 cigsd = 0.002 ++nigc = 1 poxedge = 1 pigcd = 1 ntox = 1 ++xrcrg1 = 12 xrcrg2 = 5 + ++cgso = 5e-011 cgdo = 5e-011 cgbo = 2.56e-011 cgdl = 2.653e-010 ++cgsl = 2.653e-010 ckappas = 0.03 ckappad = 0.03 acde = 1 ++moin = 15 noff = 0.9 voffcv = 0.02 + ++kt1 = -0.11 kt1l = 0 kt2 = 0.022 ute = -1.5 ++ua1 = 4.31e-009 ub1 = 7.61e-018 uc1 = -5.6e-011 prt = 0 ++at = 33000 + ++fnoimod = 1 tnoimod = 0 + ++jss = 0.0001 jsws = 1e-011 jswgs = 1e-010 njs = 1 ++ijthsfwd= 0.01 ijthsrev= 0.001 bvs = 10 xjbvs = 1 ++jsd = 0.0001 jswd = 1e-011 jswgd = 1e-010 njd = 1 ++ijthdfwd= 0.01 ijthdrev= 0.001 bvd = 10 xjbvd = 1 ++pbs = 1 cjs = 0.0005 mjs = 0.5 pbsws = 1 ++cjsws = 5e-010 mjsws = 0.33 pbswgs = 1 cjswgs = 3e-010 ++mjswgs = 0.33 pbd = 1 cjd = 0.0005 mjd = 0.5 ++pbswd = 1 cjswd = 5e-010 mjswd = 0.33 pbswgd = 1 ++cjswgd = 5e-010 mjswgd = 0.33 tpb = 0.005 tcj = 0.001 ++tpbsw = 0.005 tcjsw = 0.001 tpbswg = 0.005 tcjswg = 0.001 ++xtis = 3 xtid = 3 + ++dmcg = 0 dmci = 0 dmdg = 0 dmcgt = 0 ++dwj = 0 xgw = 0 xgl = 0 + ++rshg = 0.4 gbmin = 1e-010 rbpb = 5 rbpd = 15 ++rbps = 15 rbdb = 15 rbsb = 15 ngcon = 1 + + + diff --git a/examples/Reliability/models/65nm_bulk.pm b/examples/Reliability/models/65nm_bulk.pm new file mode 100644 index 000000000..8672a493b --- /dev/null +++ b/examples/Reliability/models/65nm_bulk.pm @@ -0,0 +1,147 @@ +* Beta Version released on 2/22/06 + +* PTM 65nm NMOS + +.model nmos nmos level = 54 + ++version = 4.8.0 binunit = 1 paramchk= 1 mobmod = 0 ++capmod = 2 igcmod = 1 igbmod = 1 geomod = 1 ++diomod = 1 rdsmod = 0 rbodymod= 1 rgatemod= 1 ++permod = 1 acnqsmod= 0 trnqsmod= 0 + ++tnom = 27 toxe = 1.85e-9 toxp = 1.2e-9 toxm = 1.85e-9 ++dtox = 0.65e-9 epsrox = 3.9 wint = 5e-009 lint = 5.25e-009 ++ll = 0 wl = 0 lln = 1 wln = 1 ++lw = 0 ww = 0 lwn = 1 wwn = 1 ++lwl = 0 wwl = 0 xpart = 0 toxref = 1.85e-9 ++xl = -30e-9 ++vth0 = 0.423 k1 = 0.4 k2 = 0.01 k3 = 0 ++k3b = 0 w0 = 2.5e-006 dvt0 = 1 dvt1 = 2 ++dvt2 = -0.032 dvt0w = 0 dvt1w = 0 dvt2w = 0 ++dsub = 0.1 minv = 0.05 voffl = 0 dvtp0 = 1.0e-009 ++dvtp1 = 0.1 lpe0 = 0 lpeb = 0 xj = 1.96e-008 ++ngate = 2e+020 ndep = 2.54e+018 nsd = 2e+020 phin = 0 ++cdsc = 0.000 cdscb = 0 cdscd = 0 cit = 0 ++voff = -0.13 nfactor = 1.9 eta0 = 0.0058 etab = 0 ++vfb = -0.55 u0 = 0.0491 ua = 6e-010 ub = 1.2e-018 ++uc = 0 vsat = 124340 a0 = 1.0 ags = 1e-020 ++a1 = 0 a2 = 1.0 b0 = 0 b1 = 0 ++keta = 0.04 dwg = 0 dwb = 0 pclm = 0.04 ++pdiblc1 = 0.001 pdiblc2 = 0.001 pdiblcb = -0.005 drout = 0.5 ++pvag = 1e-020 delta = 0.01 pscbe1 = 8.14e+008 pscbe2 = 1e-007 ++fprout = 0.2 pdits = 0.08 pditsd = 0.23 pditsl = 2.3e+006 ++rsh = 5 rdsw = 165 rsw = 85 rdw = 85 ++rdswmin = 0 rdwmin = 0 rswmin = 0 prwg = 0 ++prwb = 6.8e-011 wr = 1 alpha0 = 0.074 alpha1 = 0.005 ++beta0 = 30 agidl = 0.0002 bgidl = 2.1e+009 cgidl = 0.0002 ++egidl = 0.8 + ++aigbacc = 0.012 bigbacc = 0.0028 cigbacc = 0.002 ++nigbacc = 1 aigbinv = 0.014 bigbinv = 0.004 cigbinv = 0.004 ++eigbinv = 1.1 nigbinv = 3 aigc = 0.012 bigc = 0.0028 ++cigc = 0.002 aigsd = 0.012 bigsd = 0.0028 cigsd = 0.002 ++nigc = 1 poxedge = 1 pigcd = 1 ntox = 1 + ++xrcrg1 = 12 xrcrg2 = 5 ++cgso = 1.5e-010 cgdo = 1.5e-010 cgbo = 2.56e-011 cgdl = 2.653e-10 ++cgsl = 2.653e-10 ckappas = 0.03 ckappad = 0.03 acde = 1 ++moin = 15 noff = 0.9 voffcv = 0.02 + ++kt1 = -0.11 kt1l = 0 kt2 = 0.022 ute = -1.5 ++ua1 = 4.31e-009 ub1 = 7.61e-018 uc1 = -5.6e-011 prt = 0 ++at = 33000 + ++fnoimod = 1 tnoimod = 0 + ++jss = 0.0001 jsws = 1e-011 jswgs = 1e-010 njs = 1 ++ijthsfwd= 0.01 ijthsrev= 0.001 bvs = 10 xjbvs = 1 ++jsd = 0.0001 jswd = 1e-011 jswgd = 1e-010 njd = 1 ++ijthdfwd= 0.01 ijthdrev= 0.001 bvd = 10 xjbvd = 1 ++pbs = 1 cjs = 0.0005 mjs = 0.5 pbsws = 1 ++cjsws = 5e-010 mjsws = 0.33 pbswgs = 1 cjswgs = 3e-010 ++mjswgs = 0.33 pbd = 1 cjd = 0.0005 mjd = 0.5 ++pbswd = 1 cjswd = 5e-010 mjswd = 0.33 pbswgd = 1 ++cjswgd = 5e-010 mjswgd = 0.33 tpb = 0.005 tcj = 0.001 ++tpbsw = 0.005 tcjsw = 0.001 tpbswg = 0.005 tcjswg = 0.001 ++xtis = 3 xtid = 3 + ++dmcg = 0e-006 dmci = 0e-006 dmdg = 0e-006 dmcgt = 0e-007 ++dwj = 0.0e-008 xgw = 0e-007 xgl = 0e-008 + ++rshg = 0.4 gbmin = 1e-010 rbpb = 5 rbpd = 15 ++rbps = 15 rbdb = 15 rbsb = 15 ngcon = 1 + +* PTM 65nm PMOS + +.model pmos pmos level = 54 + ++version = 4.8.0 binunit = 1 paramchk= 1 mobmod = 0 ++capmod = 2 igcmod = 1 igbmod = 1 geomod = 1 ++diomod = 1 rdsmod = 0 rbodymod= 1 rgatemod= 1 ++permod = 1 acnqsmod= 0 trnqsmod= 0 + ++tnom = 27 toxe = 1.95e-009 toxp = 1.2e-009 toxm = 1.95e-009 ++dtox = 0.75e-9 epsrox = 3.9 wint = 5e-009 lint = 5.25e-009 ++ll = 0 wl = 0 lln = 1 wln = 1 ++lw = 0 ww = 0 lwn = 1 wwn = 1 ++lwl = 0 wwl = 0 xpart = 0 toxref = 1.95e-009 ++xl = -30e-9 ++vth0 = -0.365 k1 = 0.4 k2 = -0.01 k3 = 0 ++k3b = 0 w0 = 2.5e-006 dvt0 = 1 dvt1 = 2 ++dvt2 = -0.032 dvt0w = 0 dvt1w = 0 dvt2w = 0 ++dsub = 0.1 minv = 0.05 voffl = 0 dvtp0 = 1e-009 ++dvtp1 = 0.05 lpe0 = 0 lpeb = 0 xj = 1.96e-008 ++ngate = 2e+020 ndep = 1.87e+018 nsd = 2e+020 phin = 0 ++cdsc = 0.000 cdscb = 0 cdscd = 0 cit = 0 ++voff = -0.126 nfactor = 1.9 eta0 = 0.0058 etab = 0 ++vfb = 0.55 u0 = 0.00574 ua = 2.0e-009 ub = 0.5e-018 ++uc = 0 vsat = 70000 a0 = 1.0 ags = 1e-020 ++a1 = 0 a2 = 1 b0 = -1e-020 b1 = 0 ++keta = -0.047 dwg = 0 dwb = 0 pclm = 0.12 ++pdiblc1 = 0.001 pdiblc2 = 0.001 pdiblcb = 3.4e-008 drout = 0.56 ++pvag = 1e-020 delta = 0.01 pscbe1 = 8.14e+008 pscbe2 = 9.58e-007 ++fprout = 0.2 pdits = 0.08 pditsd = 0.23 pditsl = 2.3e+006 ++rsh = 5 rdsw = 165 rsw = 85 rdw = 85 ++rdswmin = 0 rdwmin = 0 rswmin = 0 prwg = 3.22e-008 ++prwb = 6.8e-011 wr = 1 alpha0 = 0.074 alpha1 = 0.005 ++beta0 = 30 agidl = 0.0002 bgidl = 2.1e+009 cgidl = 0.0002 ++egidl = 0.8 + ++aigbacc = 0.012 bigbacc = 0.0028 cigbacc = 0.002 ++nigbacc = 1 aigbinv = 0.014 bigbinv = 0.004 cigbinv = 0.004 ++eigbinv = 1.1 nigbinv = 3 aigc = 0.69 bigc = 0.0012 ++cigc = 0.0008 aigsd = 0.0087 bigsd = 0.0012 cigsd = 0.0008 ++nigc = 1 poxedge = 1 pigcd = 1 ntox = 1 + ++xrcrg1 = 12 xrcrg2 = 5 ++cgso = 1.5e-010 cgdo = 1.5e-010 cgbo = 2.56e-011 cgdl = 2.653e-10 ++cgsl = 2.653e-10 ckappas = 0.03 ckappad = 0.03 acde = 1 ++moin = 15 noff = 0.9 voffcv = 0.02 + ++kt1 = -0.11 kt1l = 0 kt2 = 0.022 ute = -1.5 ++ua1 = 4.31e-009 ub1 = 7.61e-018 uc1 = -5.6e-011 prt = 0 ++at = 33000 + ++fnoimod = 1 tnoimod = 0 + ++jss = 0.0001 jsws = 1e-011 jswgs = 1e-010 njs = 1 ++ijthsfwd= 0.01 ijthsrev= 0.001 bvs = 10 xjbvs = 1 ++jsd = 0.0001 jswd = 1e-011 jswgd = 1e-010 njd = 1 ++ijthdfwd= 0.01 ijthdrev= 0.001 bvd = 10 xjbvd = 1 ++pbs = 1 cjs = 0.0005 mjs = 0.5 pbsws = 1 ++cjsws = 5e-010 mjsws = 0.33 pbswgs = 1 cjswgs = 3e-010 ++mjswgs = 0.33 pbd = 1 cjd = 0.0005 mjd = 0.5 ++pbswd = 1 cjswd = 5e-010 mjswd = 0.33 pbswgd = 1 ++cjswgd = 5e-010 mjswgd = 0.33 tpb = 0.005 tcj = 0.001 ++tpbsw = 0.005 tcjsw = 0.001 tpbswg = 0.005 tcjswg = 0.001 ++xtis = 3 xtid = 3 + ++dmcg = 0e-006 dmci = 0e-006 dmdg = 0e-006 dmcgt = 0e-007 ++dwj = 0.0e-008 xgw = 0e-007 xgl = 0e-008 + ++rshg = 0.4 gbmin = 1e-010 rbpb = 5 rbpd = 15 ++rbps = 15 rbdb = 15 rbsb = 15 ngcon = 1 + + + + diff --git a/examples/Reliability/not_relan_65nm.cir b/examples/Reliability/not_relan_65nm.cir new file mode 100644 index 000000000..b8b9dba05 --- /dev/null +++ b/examples/Reliability/not_relan_65nm.cir @@ -0,0 +1,37 @@ +*not per Fra + +*.options temp=125 + +.include ./models/65nm_bulk.pm + +*.model p1_ra relmodel level=1 h_cut=b nts=c m_star=f w=g tau_0=h beta=i tau_e=j beta1=k +*.model p1_ra relmodel level=1 tau_0=5e-12 beta=0.746 +.model p1_ra relmodel level=1 type=2 +.appendmodel p1_ra pmos + +.PARAM Lmin=65n +.PARAM Wmin=65n +.PARAM Vnom=1.2 + +Mp1 OUT IN Vdd Vdd pmos L={Lmin} W={2*Wmin} +Mn1 OUT IN 0 0 nmos L={Lmin} W={Wmin} + +Cl out 0 10f + +Valim Vdd 0 {Vnom} + +Vin IN 0 pwl(0 0 2n 0 2.01n {Vnom} 4n {Vnom} 4.01n 0 6n 0 6.01n {Vnom} 8n {Vnom} 8.01n 0 10n 0 10.01n {Vnom} 12n {Vnom} 12.01n 0 14n 0 14.01n {Vnom} 16n {Vnom} ++ 16.01n 0 18n 0 18.01n {Vnom} 20n {Vnom} 20.01n 0 22n 0 22.01n {Vnom} 24n {Vnom} 24.01n 0 26n 0 26.01n {Vnom} 28n {Vnom} 28.01n 0 30n 0 30.01n {Vnom} 32n {Vnom} ++ 32.01n 0 34n 0 34.01n {Vnom} 36n {Vnom} 36.01n 0 38n 0 38.01n {Vnom} 40n {Vnom} 40.01n 0 42n 0 42.01n {Vnom} 44n {Vnom} 44.01n 0 46n 0 46.01n {Vnom} 48n {Vnom}) +*Vin IN 0 0 +*Vin IN 0 pwl(0 0 2n 0 2.01n {Vnom}) + +.relan 315360000 10p 48n +.tran 10p 48n + +.meas tran delay_LH trig v(in) val={0.5*Vnom} fall=1 targ v(out) val={0.5*Vnom} rise=1 +.meas tran delay_HL trig v(in) val={0.5*Vnom} rise=1 targ v(out) val={0.5*Vnom} fall=1 + +.control + run +.endc diff --git a/examples/Reliability/prova_relan.cir b/examples/Reliability/prova_relan.cir new file mode 100644 index 000000000..9aa27ebf5 --- /dev/null +++ b/examples/Reliability/prova_relan.cir @@ -0,0 +1,37 @@ +*not per Fra + +.include ./models/16nm_HP.pm + +*.model p1_ra relmodel level=1 h_cut=b nts=c m_star=f w=g tau_0=h beta=i tau_e=j beta1=k +*.model p1_ra relmodel level=1 tau_0=5e-12 beta=0.746 +.model p1_ra relmodel level=1 type=1 +.appendmodel p1_ra pmos + +.meas tran delay_LH trig v(in) val=0.5 fall=1 targ v(out) val=0.5 rise=1 +.meas tran delay_HL trig v(in) val=0.5 rise=1 targ v(out) val=0.5 fall=1 + +Mp1 OUT IN Vdd Vdd pmos L=22n W=44n +Mn1 OUT IN 0 0 nmos L=22n W=22n + +Cl out 0 10f + +Valim Vdd 0 0.7 +*Vin IN 0 pwl(0 0 10n 0 11n 1 60n 1 61n 0 110n 0 111n 1 160n 1 161n 0 210n 0 211n 1 260n 1 +*+ 261n 0 310n 0 311n 1 360n 1 361n 0 410n 0 411n 1 460n 1 461n 0 510n 0 511n 1 560n 1 +*+ 561n 0 610n 0 611n 1 660n 1 661n 0 710n 0 711n 1 760n 1 761n 0 810n 0 811n 1 860n 1 +*+ 861n 0) +*Vin IN 0 pwl(0 0 0.5n 0 0.501n 1 1n 1 1.01n 0 1.5n 0 1.501n 1 2n 1 2.01n 0 2.5n 0 2.501n 1 3n 1 3.01n 0 3.5n 0 3.501n 1 4n 1 +*+ 4.01n 0 4.5n 0 4.501n 1 5n 1 5.01n 0 5.5n 0 5.501n 1 6n 1 6.01n 0 6.5n 0 6.501n 1 7n 1 7.01n 0 7.5n 0 7.501n 1 8n 1 +*+ 8.01n 0 8.5n 0 8.501n 1 9n 1 9.01n 0 9.5n 0 9.501n 1 10n 1) +Vin IN 0 pwl(0 0 2n 0 2.01n 0.7 4n 0.7 4.01n 0 6n 0 6.01n 0.7 8n 0.7 8.01n 0 10n 0 10.01n 0.7 12n 0.7 12.01n 0 14n 0 14.01n 0.7 16n 0.7 ++ 16.01n 0 18n 0 18.01n 0.7 20n 0.7 20.01n 0 22n 0 22.01n 0.7 24n 0.7 24.01n 0 26n 0 26.01n 0.7 28n 0.7 28.01n 0 30n 0 30.01n 0.7 32n 0.7 ++ 32.01n 0 34n 0 34.01n 0.7 36n 0.7 36.01n 0 38n 0 38.01n 0.7 40n 0.7 40.01n 0 42n 0 42.01n 0.7 44n 0.7 44.01n 0 46n 0 46.01n 0.7 48n 0.7) +*Vin IN 0 pwl(0 0 10n 0) +*Vin IN 0 pwl(0 1 10n 1) + +.relan 315360000 10p 48n +.tran 10p 48n + +.control + run +.endc diff --git a/examples/Reliability/subckt/sottocircuiti b/examples/Reliability/subckt/sottocircuiti new file mode 100644 index 000000000..98548f3bc --- /dev/null +++ b/examples/Reliability/subckt/sottocircuiti @@ -0,0 +1,906 @@ +************************************************************************************************ +*esempi +*xnand1 0 node1 nodeZ nodeA nodeB NAND2_SUB <--drive strength di default=1 +*xnand2 0 node1 nodeZ nodeA nodeB NAND2_SUB XX=2 <--drive strength =2 +*xxor1 0 node1 nodeZ nodeB nodeA XOR2_SUB + + +.subckt NOT4_SUB 1 2 3 4 XX=4 +Mn1 3 4 1 1 nmos W={1*XX*Wmin} L={Lmin} +Mp1 3 4 2 2 pmos W={2*XX*Wmin} L={Lmin} +.ends + + + + +************************************************************************************************ +* not +************************************************************************************************ +* devono essere dichiarate nel listato chiamante Wmin, Lmin ed il modello per i mos +* +*drive strength ---------+ +*inA -----------------+ | +*uscita ------------+ | | +*vdd -------------+ | | | +*massa ---------+ | | | | +* | | | | | +* v v v v v +.subckt NOT_SUB 1 2 3 4 XX=1 +Mn1 3 4 1 1 nmos W={1*XX*Wmin} L={Lmin} +Mp1 3 4 2 2 pmos W={2*XX*Wmin} L={Lmin} +.ends +************************************************************************************************ + +************************************************************************************************ +* nand2 +************************************************************************************************ +* devono essere dichiarate nel listato chiamante Wmin, Lmin ed il modello per i mos + +*drive strength ------------+ +*inB ----mos uscita-------+ | +*inA ----mos massa------+ | | +*uscita --------------+ | | | +*vdd ---------------+ | | | | +*massa -----------+ | | | | | +* | | | | | | +* v v v v v v +.subckt NAND2_SUB 1 2 3 4 5 XX=1 +Mn1 6 4 1 1 nmos W={2*XX*Wmin} L={Lmin} +Mn2 3 5 6 1 nmos W={2*XX*Wmin} L={Lmin} +Mp1 3 4 2 2 pmos W={2*XX*Wmin} L={Lmin} +Mp2 3 5 2 2 pmos W={2*XX*Wmin} L={Lmin} +.ends +************************************************************************************************ + +************************************************************************************************ +* nand3 +************************************************************************************************ +*drive strength---------------+ +*inC------------------------+ | +*inB ---------------------+ | | +*inA -------------------+ | | | +*output --------------+ | | | | +*vdd ---------------+ | | | | | +*ground-----------+ | | | | | | +* | | | | | | | +* v v v v v v v +.subckt NAND3_SUB 1 2 3 4 5 6 XX=1 +Mn1 7 4 1 1 nmos W={3*XX*Wmin} L={Lmin} +Mn2 8 5 7 1 nmos W={3*XX*Wmin} L={Lmin} +Mn3 3 6 8 1 nmos W={3*XX*Wmin} L={Lmin} + +Mp1 3 4 2 2 pmos W={2*XX*Wmin} L={Lmin} +Mp2 3 5 2 2 pmos W={2*XX*Wmin} L={Lmin} +Mp3 3 6 2 2 pmos W={2*XX*Wmin} L={Lmin} +.ends +************************************************************************************************ + +************************************************************************************************ +* nand4 +************************************************************************************************ +*drive strengh------------------+ +*inD--------------------------+ | +*inC------------------------+ | | +*inB ---------------------+ | | | +*inA -------------------+ | | | | +*output --------------+ | | | | | +*vdd ---------------+ | | | | | | +*ground-----------+ | | | | | | | +* | | | | | | | | +* v v v v v v v v +.subckt NAND4_SUB 1 2 3 4 5 6 7 XX=1 +Mn1 8 4 1 1 nmos W={4*XX*Wmin} L={Lmin} +Mn2 9 5 8 1 nmos W={4*XX*Wmin} L={Lmin} +Mn3 10 6 9 1 nmos W={4*XX*Wmin} L={Lmin} +Mn4 3 7 10 1 nmos W={4*XX*Wmin} L={Lmin} + +Mp1 3 4 2 2 pmos W={2*XX*Wmin} L={Lmin} +Mp2 3 5 2 2 pmos W={2*XX*Wmin} L={Lmin} +Mp3 3 6 2 2 pmos W={2*XX*Wmin} L={Lmin} +Mp4 3 7 2 2 pmos W={2*XX*Wmin} L={Lmin} + +.ends +************************************************************************************************ + +************************************************************************************************ +* nor2 +************************************************************************************************ +* devono essere dichiarate nel listato chiamante Wmin, Lmin ed il modello per i mos + +*drive strength -----------+ +*inB ---mos uscita-------+ | +*inA ---mos vdd--------+ | | +*uscita -------------+ | | | +*vdd --------------+ | | | | +*massa ----------+ | | | | | +* | | | | | | +* v v v v v v +.subckt NOR2_SUB 1 2 3 4 5 XX=1 +Mn1 3 4 1 1 nmos W={1*XX*Wmin} L={Lmin} +Mn2 3 5 1 1 nmos W={1*XX*Wmin} L={Lmin} +Mp1 6 4 2 2 pmos W={4*XX*Wmin} L={Lmin} +Mp2 3 5 6 2 pmos W={4*XX*Wmin} L={Lmin} +.ends +************************************************************************************************ + +************************************************************************************************ +* nor3 +************************************************************************************************ +* devono essere dichiarate nel listato chiamante Wmin, Lmin ed il modello per i mos +* +*drive strenght--------------+ +*inC--- -------------------+ | +*inB --------------------+ | | +*inA ------------------+ | | | +*output -------------+ | | | | +*vdd --------------+ | | | | | +*ground----------+ | | | | | | +* | | | | | | | +* v v v v v v v +.subckt NOR3_SUB 1 2 3 4 5 6 XX=1 + +Mn1 3 4 1 1 nmos W={1*XX*Wmin} L={Lmin} +Mn2 3 5 1 1 nmos W={1*XX*Wmin} L={Lmin} +Mn3 3 6 1 1 nmos W={1*XX*Wmin} L={Lmin} +Mp1 7 4 2 2 pmos W={6*XX*Wmin} L={Lmin} +Mp2 8 5 7 2 pmos W={6*XX*Wmin} L={Lmin} +Mp3 3 6 8 2 pmos W={6*XX*Wmin} L={Lmin} + +.ends +************************************************************************************************ + +************************************************************************************************ +* nor4 +************************************************************************************************ +* devono essere dichiarate nel listato chiamante Wmin, Lmin ed il modello per i mos +* +*drive strenght------------------+ +*in4-------------------------+ | +*in3--- -------------------+ | | +*in2 --------------------+ | | | +*in1 ------------------+ | | | | +*output -------------+ | | | | | +*vdd --------------+ | | | | | | +*ground----------+ | | | | | | | +* | | | | | | | | +* v v v v v v v v +.subckt NOR4_SUB 1 2 3 4 5 6 7 XX=1 +Mn1 3 4 1 1 nmos W={1*XX*Wmin} L={Lmin} +Mn2 3 5 1 1 nmos W={1*XX*Wmin} L={Lmin} +Mn3 3 6 1 1 nmos W={1*XX*Wmin} L={Lmin} +Mn4 3 7 1 1 nmos W={1*XX*Wmin} L={Lmin} +Mp1 10 4 2 2 pmos W={8*XX*Wmin} L={Lmin} +Mp2 9 5 10 2 pmos W={8*XX*Wmin} L={Lmin} +Mp3 8 6 9 2 pmos W={8*XX*Wmin} L={Lmin} +Mp4 3 7 8 2 pmos W={8*XX*Wmin} L={Lmin} + +.ends +************************************************************************************************ + +************************************************************************************************ +* xor2 +************************************************************************************************ +* devono essere dichiarate nel listato chiamante Wmin, Lmin ed il modello per i mos +* +*drive strength -------------+ +*inB --------------------+ | +*inA ------------------+ | | +*uscita -------------+ | | | +*vdd --------------+ | | | | +*massa ----------+ | | | | | +* | | | | | | +* v v v v v v +.subckt XOR2_SUB 1 2 3 4 5 XX=1 +*NOT +Mp5 node5n 5 2 2 pmos L={Lmin} W={2*XX*Wmin} +Mn5 node5n 5 1 1 nmos L={Lmin} W={XX*Wmin} +Mp6 node4n 4 2 2 pmos L={Lmin} W={2*XX*Wmin} +Mn6 node4n 4 1 1 nmos L={Lmin} W={XX*Wmin} + +*PULL UP +Mp1 3 4 int4 2 pmos L={Lmin} W={4*XX*Wmin} +Mp2 3 node4n int1 2 pmos L={Lmin} W={4*XX*Wmin} +Mp3 int4 node5n 2 2 pmos L={Lmin} W={4*XX*Wmin} +Mp4 int1 5 2 2 pmos L={Lmin} W={4*XX*Wmin} + +*PULL DOWN +Mn4 6 4 1 1 nmos L={Lmin} W={2*XX*Wmin} +Mn3 3 5 6 1 nmos L={Lmin} W={2*XX*Wmin} +Mn2 int3 node4n 1 1 nmos L={Lmin} W={2*XX*Wmin} +Mn1 3 node5n int3 1 nmos L={Lmin} W={2*XX*Wmin} +.ends +************************************************************************************************ + +************************************************************************************************ +* and2 +************************************************************************************************ +* devono essere dichiarate nel listato chiamante Wmin, Lmin ed il modello per i mos +* +*drive strength--------------+ +*inB ----mos uscita-------+ | +*inA ----mos massa------+ | | +*uscita --------------+ | | | +*vdd ---------------+ | | | | +*massa -----------+ | | | | | +* | | | | | | +* v v v v v v +.subckt AND2_SUB 1 2 3 4 5 XX=1 +Mn1 6 4 1 1 nmos W={2*XX*Wmin} L={Lmin} +Mn2 7 5 6 1 nmos W={2*XX*Wmin} L={Lmin} +Mp1 7 4 2 2 pmos W={2*XX*Wmin} L={Lmin} +Mp2 7 5 2 2 pmos W={2*XX*Wmin} L={Lmin} + +Mp3 3 7 2 2 pmos W={2*XX*Wmin} L={Lmin} +Mn3 3 7 1 1 nmos W={1*XX*Wmin} L={Lmin} + +.ends +************************************************************************************************ + +************************************************************************************************ +* and3 +************************************************************************************************ +* devono essere dichiarate nel listato chiamante Wmin, Lmin ed il modello per i mos +* +*drive strength----------------+ +*inC------------------------+ | +*inB ----mos output-------+ | | +*inA ----mos ground-----+ | | | +*output --------------+ | | | | +*vdd ---------------+ | | | | | +*groung-----------+ | | | | | | +* | | | | | | | +* v v v v v v v +.subckt AND3_SUB 1 2 3 4 5 6 XX=1 + +Mn1 7 4 1 1 nmos W={3*XX*Wmin} L={Lmin} +Mn2 8 5 7 1 nmos W={3*XX*Wmin} L={Lmin} +Mn3 9 6 8 1 nmos W={3*XX*Wmin} L={Lmin} +Mp1 9 4 2 2 pmos W={2*XX*Wmin} L={Lmin} +Mp2 9 5 2 2 pmos W={2*XX*Wmin} L={Lmin} +Mp3 9 6 2 2 pmos W={2*XX*Wmin} L={Lmin} + +Mp4 3 9 2 2 pmos W={2*XX*Wmin} L={Lmin} +Mn4 3 9 1 1 nmos W={1*XX*Wmin} L={Lmin} + +.ends +************************************************************************************************ + +************************************************************************************************ +* and4 +************************************************************************************************ +* devono essere dichiarate nel listato chiamante Wmin, Lmin ed il modello per i mos +* +*drive strength------------------+ +*inD--------------------------+ | +*inC------------------------+ | | +*inB ----mos output-------+ | | | +*inA ----mos ground-----+ | | | | +*output --------------+ | | | | | +*vdd ---------------+ | | | | | | +*groung-----------+ | | | | | | | +* | | | | | | | | +* v v v v v v v v +.subckt AND4_SUB 1 2 3 4 5 6 7 XX=1 + +Mn1 10 4 1 1 nmos W={4*XX*Wmin} L={Lmin} +Mn2 9 5 10 1 nmos W={4*XX*Wmin} L={Lmin} +Mn3 8 6 9 1 nmos W={4*XX*Wmin} L={Lmin} +Mn4 11 7 8 1 nmos W={4*XX*Wmin} L={Lmin} + +Mp1 11 4 2 2 pmos W={2*XX*Wmin} L={Lmin} +Mp2 11 5 2 2 pmos W={2*XX*Wmin} L={Lmin} +Mp3 11 6 2 2 pmos W={2*XX*Wmin} L={Lmin} +Mp4 11 7 2 2 pmos W={2*XX*Wmin} L={Lmin} + +Mp5 3 11 2 2 pmos W={2*XX*Wmin} L={Lmin} +Mn5 3 11 1 1 nmos W={1*XX*Wmin} L={Lmin} + +.ends +************************************************************************************************ + +************************************************************************************************ +* mux21 +************************************************************************************************ +*drive strength--------------------------------------+ +*inC-(nodeS0)---------------------------------+ | +*inB-(nodeD1)---------------------------+ | | +*inA-(nodeD0)---------------------+ | | | +*output---------------------+ | | | | +*vdd -----------------+ | | | | | +*ground-----------+ | | | | | | +* | | | | | | | +* v v v v v v v +.subckt mux21_SUB 0 node1 nodez nodea nodeb nodec XX=1 + +*RETE PASS TRANSISTOR +Mn4 nodea nodecn nodeu 0 nmos W={2*XX*Wmin} L={Lmin} +Mn5 nodeb nodec nodeu 0 nmos W={2*XX*Wmin} L={Lmin} +Mp4 nodea nodec nodeu node1 pmos W={2*XX*Wmin} L={Lmin} +Mp5 nodeb nodecn nodeu node1 pmos W={2*XX*Wmin} L={Lmin} + +*INVERTER FINALI +Mn3 nodez nodeun 0 0 nmos W={XX*Wmin} L={Lmin} +Mp3 nodez nodeun node1 node1 pmos W={2*XX*Wmin} L={Lmin} +Mn2 nodeun nodeu 0 0 nmos W={XX*Wmin} L={Lmin} +Mp2 nodeun nodeu node1 node1 pmos W={2*XX*Wmin} L={Lmin} + +*NOT +Mp1 nodecn nodec node1 node1 pmos W={2*XX*Wmin} L={Lmin} +Mn1 nodecn nodec 0 0 nmos W={XX*Wmin} L={Lmin} +.ends + +************************************************************************************************ + +************************************************************************************************ +* mux31 +************************************************************************************************ +*drive strength----------------------------------------------------+ +*in5-(nodeS1)----------------------------------------------+ | +*in4-(nodeS0)----------------------------------------+ | | +*in3-(nodeD2)---------------------------------+ | | | +*in2-(nodeD1)---------------------------+ | | | | +*in1-(nodeD0)---------------------+ | | | | | +*output---------------------+ | | | | | | +*vdd -----------------+ | | | | | | | +*ground-----------+ | | | | | | | | +* | | | | | | | | | +* v v v v v v v v v +.subckt mux31_SUB 0 node1 nodeZ nodeA nodeB nodeC nodeD nodeE XX=1 + +Mp8 nodeU1 nodee nodeU2 node1 pmos W={3*XX*Wmin} L={Lmin} +Mp3 nodea noded nodeU1 node1 pmos W={3*XX*Wmin} L={Lmin} +Mp2 nodeeN nodee node1 node1 pmos W={2*XX*Wmin} L={Lmin} +Mp1 nodedN noded node1 node1 pmos W={2*XX*Wmin} L={Lmin} +Mp4 nodeb nodedN nodeU1 node1 pmos W={3*XX*Wmin} L={Lmin} +Mn3 nodea nodedN nodeU1 0 nmos W={3*XX*Wmin} L={Lmin} +Mn8 nodeU1 nodeeN nodeU2 0 nmos W={3*XX*Wmin} L={Lmin} +Mn4 nodeb noded nodeU1 0 nmos W={3*XX*Wmin} L={Lmin} + +Mn7 nodez 1 0 0 nmos W={XX*Wmin} L={Lmin} +Mp7 nodez 1 node1 node1 pmos W={2*XX*Wmin} L={Lmin} +Mn6 1 nodeU2 0 0 nmos W={XX*Wmin} L={Lmin} + +Mp6 1 nodeU2 node1 node1 pmos W={2*XX*Wmin} L={Lmin} +Mp5 nodec nodeeN nodeU2 node1 pmos W={2*XX*Wmin} L={Lmin} +Mn2 nodeeN nodee 0 0 nmos W={XX*Wmin} L={Lmin} + +Mn1 nodedN noded 0 0 nmos W={XX*Wmin} L={Lmin} +Mn5 nodec nodee nodeU2 0 nmos W={2*XX*Wmin} L={Lmin} + +.ends +************************************************************************************************ + +************************************************************************************************ +* mux41 +************************************************************************************************ +*drive strength--------------------------------------------------------+ +*in6-(nodeS1)--------------------------------------------------+ | +*in5-(nodeS0)----------------------------------------------+ | | +*in4-(nodeD3)----------------------------------------+ | | | +*in3-(nodeD2)---------------------------------+ | | | | +*in2-(nodeD1)---------------------------+ | | | | | +*in1-(nodeD0)---------------------+ | | | | | | +*output---------------------+ | | | | | | | +*vdd -----------------+ | | | | | | | | +*ground-----------+ | | | | | | | | | +* | | | | | | | | | | +* v v v v v v v v v v +.subckt mux41_SUB 0 node1 nodeZ nodeA nodeB nodeC nodeD nodeE nodeF XX=1 + +Mn1 nodeeN nodee 0 0 nmos W={XX*Wmin} L={Lmin} +Mp1 nodeeN nodee node1 node1 pmos W={2*XX*Wmin} L={Lmin} +Mn2 nodefN nodef 0 0 nmos W={XX*Wmin} L={Lmin} +Mp2 nodefN nodef node1 node1 pmos W={2*XX*Wmin} L={Lmin} +Mp3 nodea nodee nodeU1 node1 pmos W={3*XX*Wmin} L={Lmin} +Mn3 nodea nodeeN nodeU1 0 nmos W={3*XX*Wmin} L={Lmin} +Mn4 nodeb nodee nodeU1 0 nmos W={3*XX*Wmin} L={Lmin} +Mp4 nodeb nodeeN nodeU1 node1 pmos W={3*XX*Wmin} L={Lmin} +Mp5 nodec nodee nodeU2 node1 pmos W={3*XX*Wmin} L={Lmin} +Mn5 nodec nodeeN nodeU2 0 nmos W={3*XX*Wmin} L={Lmin} +Mp6 noded nodeeN nodeU2 node1 pmos W={3*XX*Wmin} L={Lmin} +Mn6 noded nodee nodeU2 0 nmos W={3*XX*Wmin} L={Lmin} +Mp7 nodeU1 nodef nodez node1 pmos W={3*XX*Wmin} L={Lmin} +Mn7 nodeU1 nodefN nodeU3 0 nmos W={3*XX*Wmin} L={Lmin} +Mp8 nodeU2 nodefN nodez node1 pmos W={3*XX*Wmin} L={Lmin} +Mn8 nodeU2 nodef nodeU3 0 nmos W={3*XX*Wmin} L={Lmin} + +Mp9 1 nodeU3 node1 node1 pmos W={2*XX*Wmin} L={Lmin} +Mn9 1 nodeU3 0 0 nmos W={XX*Wmin} L={Lmin} + +Mn10 nodez 1 0 0 nmos W={XX*Wmin} L={Lmin} +Mp10 nodez 1 node1 node1 pmos W={2*XX*Wmin} L={Lmin} +.ends +************************************************************************************************ + +************************************************************************************************ +* DLatch +************************************************************************************************ +*drive strength--------------------------------+ +*inB ---(like i/p)-nodeD-----------------+ | +*inA ---(like clk)-nodeG-----------+ | | +*output----------------------+ | | | +*vdd ------------------+ | | | | +*ground------------+ | | | | | +* | | | | | | +* v v v v v v +.subckt DLatch_SUB 0 node1 nodeZ nodea nodeb XX=1 + +Mp41 nodeb nodeaN node21 node1 pmos W={2*XX*Wmin} L={Lmin} +Mn4 nodeb nodea node21 0 nmos W={2*XX*Wmin} L={Lmin} +Mn3 nodez 1 0 0 nmos W={XX*Wmin} L={Lmin} +Mp3 nodez 1 node1 node1 pmos W={2*XX*Wmin} L={Lmin} + +*REAZIONE + +Mn1 node21 1 0 0 nmos W={XX*Wmin} L={2*Lmin} +Mp1 node21 1 node1 node1 pmos W={XX*Wmin} L={2*Lmin} +Mn2 1 node21 0 0 nmos W={1*XX*Wmin} L={Lmin} +Mp2 1 node21 node1 node1 pmos W={2*XX*Wmin} L={Lmin} + +*G NEGATO +Mp5 nodeaN nodea node1 node1 pmos W={2*XX*Wmin} L={Lmin} +Mn5 nodeaN nodea 0 0 nmos W={XX*Wmin} L={Lmin} +.ends +************************************************************************************************ + +************************************************************************************************ +* AO12 +************************************************************************************************ +* devono essere dichiarate nel listato chiamante Wmin, Lmin ed il modello per i mos +* +*drive strength---------------+ +*inC ----mos out-gnd--------+ | +*inB ----mos Vdd-gnd------+ | | +*inA ----mos Vdd-out----+ | | | +*uscita --------------+ | | | | +*vdd ---------------+ | | | | | +*massa -----------+ | | | | | | +* | | | | | | | +* v v v v v v v +.subckt AO12_SUB 1 2 3 4 5 6 XX=1 +Mn1 9 4 8 1 nmos W={2*XX*Wmin} L={Lmin} +Mn2 8 5 1 1 nmos W={2*XX*Wmin} L={Lmin} +Mn3 9 6 1 1 nmos W={1*XX*Wmin} L={Lmin} + +Mp1 7 4 2 2 pmos W={4*XX*Wmin} L={Lmin} +Mp2 7 5 2 2 pmos W={4*XX*Wmin} L={Lmin} +Mp3 9 6 7 2 pmos W={4*XX*Wmin} L={Lmin} + +Mn4 3 9 1 1 nmos W={XX*Wmin} L={Lmin} +Mp4 3 9 2 2 pmos W={2*XX*Wmin} L={Lmin} +.ends +************************************************************************************************ + +************************************************************************************************ +* AO22 +************************************************************************************************ +* devono essere dichiarate nel listato chiamante Wmin, Lmin ed il modello per i mos +* +*drive strength-----------------+ +*inD ----mos Vdd-gnd----------+ | +*inC ----mos Vdd-out--------+ | | +*inB ----mos out-gnd------+ | | | +*inA ----mos out-out----+ | | | | +*uscita --------------+ | | | | | +*vdd ---------------+ | | | | | | +*massa -----------+ | | | | | | | +* | | | | | | | | +* v v v v v v v v +.subckt AO22_SUB 1 2 3 4 5 6 7 XX=1 +* D G S B Name W L +*PULL DOWN +Mn1 11 4 9 1 nmos W={2*XX*Wmin} L={Lmin} +Mn2 9 5 1 1 nmos W={2*XX*Wmin} L={Lmin} + +Mn3 11 6 10 1 nmos W={2*XX*Wmin} L={Lmin} +Mn4 10 7 1 1 nmos W={2*XX*Wmin} L={Lmin} + +*PULL UP +Mp1 11 4 8 2 pmos w={4*XX*Wmin} L={Lmin} +Mp2 11 5 8 2 pmos W={4*XX*Wmin} L={Lmin} + +Mp3 8 6 2 2 pmos W={4*XX*Wmin} L={Lmin} +Mp4 8 7 2 2 pmos W={4*XX*Wmin} L={Lmin} + +*USCITA +Mn5 3 11 1 1 nmos W={Wmin} L={Lmin} +Mp5 3 11 2 2 pmos W={2*Wmin} L={Lmin} + +.ends +************************************************************************************************ + +************************************************************************************************ +* AO31 +************************************************************************************************ +* devono essere dichiarate nel listato chiamante Wmin, Lmin ed il modello per i mos +* +*drive strength---------------------+ +*inD ----mos out-out--------------+ | +*inC ----mos Vdd-gnd------------+ | | +*inB ----mos Vdd-mid,mid------+ | | | +*inA ----mos Vdd-out--------+ | | | | +*uscita ------------------+ | | | | | +*vdd -------------------+ | | | | | | +*massa ---------------+ | | | | | | | +* | | | | | | | | +* v v v v v v v v +.subckt AO31_SUB 1 2 3 4 5 6 7 XX=1 +* D G S B Name W L + +Mn1 9 4 10 1 nmos W={3*XX*Wmin} L={Lmin} +Mn2 10 5 11 1 nmos W={3*XX*Wmin} L={Lmin} +Mn3 11 6 1 1 nmos W={3*XX*Wmin} L={Lmin} +Mn4 9 7 1 1 nmos W={1*XX*Wmin} L={Lmin} + +Mp1 8 4 2 2 pmos W={4*XX*Wmin} L={Lmin} +Mp2 8 5 2 2 pmos W={4*XX*Wmin} L={Lmin} +Mp3 8 6 2 2 pmos W={4*XX*Wmin} L={Lmin} +Mp4 9 7 8 2 pmos W={4*XX*Wmin} L={Lmin} + +Mn5 3 9 1 1 nmos W={1*XX*Wmin} L={Lmin} +Mp5 3 9 2 2 pmos W={2*XX*Wmin} L={Lmin} +.ends +************************************************************************************************ + +************************************************************************************************ +* AO32 +************************************************************************************************ +* devono essere dichiarate nel listato chiamante Wmin, Lmin ed il modello per i mos +* +*drive strength------------------------+ +*inE ----mos out-gnd----------------+ | +*inD ----mos out-out--------------+ | | +*inC ----mos Vdd-gnd------------+ | | | +*inB ----mos Vdd-mid,mid------+ | | | | +*inA ----mos Vdd-out--------+ | | | | | +*uscita ------------------+ | | | | | | +*vdd -------------------+ | | | | | | | +*massa ---------------+ | | | | | | | | +* | | | | | | | | | +* v v v v v v v v V +.subckt AO32_SUB 1 2 3 4 5 6 7 8 XX=1 +* D G S B Name W L + +Mn6 3 10 1 1 nmos W={XX*Wmin} L={Lmin} +Mp6 3 10 2 2 pmos W={2*XX*Wmin} L={Lmin} + +Mn1 10 4 11 1 nmos W={3*XX*Wmin} L={Lmin} +Mn2 11 5 12 1 nmos W={3*XX*Wmin} L={Lmin} +Mn3 12 6 1 1 nmos W={3*XX*Wmin} L={Lmin} +Mn4 10 7 13 1 nmos W={2*XX*Wmin} L={Lmin} +Mn5 13 8 1 1 nmos W={2*XX*Wmin} L={Lmin} + +Mp1 10 7 9 2 pmos W={4*XX*Wmin} L={Lmin} +Mp2 10 8 9 2 pmos W={4*XX*Wmin} L={Lmin} +Mp3 9 4 2 2 pmos W={4*XX*Wmin} L={Lmin} +Mp4 9 5 2 2 pmos W={4*XX*Wmin} L={Lmin} +Mp5 9 6 2 2 pmos W={4*XX*Wmin} L={Lmin} + +.ends +************************************************************************************************ + +************************************************************************************************ +* AO33 +************************************************************************************************ +* devono essere dichiarate nel listato chiamante Wmin, Lmin ed il modello per i mos +* +*drive strength--------------------------+ +*inF ----mos out-gnd------------------+ | +*inE ----mos out-mid,mid------------+ | | +*inD ----mos out-out--------------+ | | | +*inC ----mos Vdd-gnd------------+ | | | | +*inB ----mos Vdd-mid,mid------+ | | | | | +*inA ----mos Vdd-out--------+ | | | | | | +*uscita ------------------+ | | | | | | | +*vdd -------------------+ | | | | | | | | +*massa ---------------+ | | | | | | | | | +* | | | | | | | | | | +* v v v v v v v v v v +.subckt AO33_SUB 1 2 3 4 5 6 7 8 9 XX=1 +* D G S B Name W L +Mn1 11 4 12 1 nmos W={3*XX*Wmin} L={Lmin} +Mn2 12 5 13 1 nmos W={3*XX*Wmin} L={Lmin} +Mn3 13 6 1 1 nmos W={3*XX*Wmin} L={Lmin} +Mn4 11 7 14 1 nmos W={3*XX*Wmin} L={Lmin} +Mn5 14 8 15 1 nmos W={3*XX*Wmin} L={Lmin} +Mn6 15 9 1 1 nmos W={3*XX*Wmin} L={Lmin} + +Mp1 10 4 2 2 pmos W={4*XX*Wmin} L={Lmin} +Mp2 10 5 2 2 pmos W={4*XX*Wmin} L={Lmin} +Mp3 10 6 2 2 pmos W={4*XX*Wmin} L={Lmin} +Mp4 11 7 10 2 pmos W={4*XX*Wmin} L={Lmin} +Mp5 11 8 10 2 pmos W={4*XX*Wmin} L={Lmin} +Mp6 11 9 10 2 pmos W={4*XX*Wmin} L={Lmin} + +Mn7 3 11 1 1 nmos W={XX*Wmin} L={Lmin} +Mp7 3 11 2 2 pmos W={2*XX*Wmin} L={Lmin} +.ends +************************************************************************************************ + +************************************************************************************************ +* AO112 +************************************************************************************************ +* devono essere dichiarate nel listato chiamante Wmin, Lmin ed il modello per i mos +* +*drive strength---------------------+ +*inD ----mos out-out--------------+ | +*inC ----mos mid,mid-gnd--------+ | | +*inB ----mos Vdd-gnd----------+ | | | +*inA ----mos Vdd-out--------+ | | | | +*uscita ------------------+ | | | | | +*vdd -------------------+ | | | | | | +*massa ---------------+ | | | | | | | +* | | | | | | | | +* v v v v v v v v +.subckt AO112_SUB 1 2 3 4 5 6 7 XX=1 +* D G S B Name W L + +Mn1 10 4 11 1 nmos W={2*XX*Wmin} L={Lmin} +Mn2 11 5 1 1 nmos W={2*XX*Wmin} L={Lmin} +Mn3 10 6 1 1 nmos W={1*XX*Wmin} L={Lmin} +Mn4 10 7 1 1 nmos W={1*XX*Wmin} L={Lmin} + +Mp1 8 4 2 2 pmos W={6*XX*Wmin} L={Lmin} +Mp2 8 5 2 2 pmos W={6*XX*Wmin} L={Lmin} +Mp3 9 6 8 2 pmos W={6*XX*Wmin} L={Lmin} +Mp4 10 7 9 2 pmos W={6*XX*Wmin} L={Lmin} + +Mn5 3 10 1 1 nmos W={XX*Wmin} L={Lmin} +Mp5 3 10 2 2 pmos W={2*XX*Wmin} L={Lmin} +.ends +************************************************************************************************ + +************************************************************************************************ +* AO212 +************************************************************************************************ +* devono essere dichiarate nel listato chiamante Wmin, Lmin ed il modello per i mos +* +*drive strength-----------------------+ +*inE ----mos out-gnd----------------+ | +*inD ----mos Vdd-gnd--------------+ | | +*inC ----mos Vdd-out------------+ | | | +*inB ----mos mid,mid-gnd------+ | | | | +*inA ----mos Vdd-out--------+ | | | | | +*uscita ------------------+ | | | | | | +*vdd -------------------+ | | | | | | | +*massa ---------------+ | | | | | | | | +* | | | | | | | | | +* v v v v v v v v v +.subckt AO212_SUB 1 2 3 4 5 6 7 8 XX=1 +* D G S B Name W L + +Mn1 12 4 13 1 nmos W={2*XX*Wmin} L={Lmin} +Mn2 13 5 1 1 nmos W={2*XX*Wmin} L={Lmin} +Mn3 12 6 14 1 nmos W={2*XX*Wmin} L={Lmin} +Mn4 14 7 1 1 nmos W={2*XX*Wmin} L={Lmin} +Mn5 12 8 1 1 nmos W={XX*Wmin} L={Lmin} + +Mp1 11 4 9 2 pmos W={6*XX*Wmin} L={Lmin} +Mp2 11 5 9 2 pmos W={6*XX*Wmin} L={Lmin} +Mp3 9 6 2 2 pmos W={6*XX*Wmin} L={Lmin} +Mp4 9 7 2 2 pmos W={6*XX*Wmin} L={Lmin} +Mp5 12 8 11 2 pmos W={6*XX*Wmin} L={Lmin} + +Mn7 3 12 1 1 nmos W={XX*Wmin} L={Lmin} +Mp7 3 12 2 2 pmos W={2*XX*Wmin} L={Lmin} + +.ends +************************************************************************************************* + +************************************************************************************************* +* AO222 +************************************************************************************************* +* devono essere dichiarate nel listato chiamante Wmin, Lmin ed il modello per i mos +* +*drive strength-------------------------+ +*inF ----mos Vdd-gnd------------------+ | +*inE ----mos Vdd-out----------------+ | | +*inD ----mos mid,mid-gnd----------+ | | | +*inC ----mos mid,mid-out--------+ | | | | +*inB ----mos out-gnd----------+ | | | | | +*inA ----mos out-out--------+ | | | | | | +*uscita ------------------+ | | | | | | | +*vdd -------------------+ | | | | | | | | +*massa ---------------+ | | | | | | | | | +* | | | | | | | | | | +* v v v v v v v v v v +.subckt AO222_SUB 1 2 3 4 5 6 7 8 9 XX=1 +* D G S B Name W L + +Mn1 12 4 13 1 nmos W={2*XX*Wmin} L={Lmin} +Mn2 13 5 1 1 nmos W={2*XX*Wmin} L={Lmin} +Mn3 12 6 14 1 nmos W={2*XX*Wmin} L={Lmin} +Mn4 14 7 1 1 nmos W={2*XX*Wmin} L={Lmin} +Mn5 12 8 15 1 nmos W={2*XX*Wmin} L={Lmin} +Mn6 15 9 1 1 nmos W={2*XX*Wmin} L={Lmin} + +Mp1 12 4 11 2 pmos W={6*XX*Wmin} L={Lmin} +Mp2 12 5 11 2 pmos W={6*XX*Wmin} L={Lmin} +Mp3 11 6 10 2 pmos W={6*XX*Wmin} L={Lmin} +Mp4 11 7 10 2 pmos W={6*XX*Wmin} L={Lmin} +Mp5 10 8 2 2 pmos W={6*XX*Wmin} L={Lmin} +Mp6 10 9 2 2 pmos W={6*XX*Wmin} L={Lmin} + +Mn7 3 12 1 1 nmos W={XX*Wmin} L={Lmin} +Mp7 3 12 2 2 pmos W={2*XX*Wmin} L={Lmin} + +.ends +************************************************************************************************ + +************************************************************************************************ +* DFPQ +************************************************************************************************ +*drive strength---------------------------------+ +*inB ---(like i/p)-nodeD------------------+ | +*inA ---(like clk)-nodeA-----------+ | | +*output----------------------+ | | | +*vdd ------------------+ | | | | +*ground------------+ | | | | | +* | | | | | | +* v v v v v v +.subckt DFPQ_SUB 0 node1 nodeZ nodeCP noded XX=1 + +Mp41 noded nodeCP node21 node1 pmos W={2*XX*Wmin} L={Lmin} +Mn4 noded nodeCPn node21 0 nmos W={2*XX*Wmin} L={Lmin} + +Mn5 noded5 nodeCP node51 0 nmos W={2*XX*Wmin} L={Lmin} +Mp51 noded5 nodeCPn node51 node1 pmos W={2*XX*Wmin} L={Lmin} + +Mn11 nodeCPn nodeCP 0 0 nmos W={1*XX*Wmin} L={Lmin} +Mp11 nodeCPn nodeCP node1 node1 pmos W={2*XX*Wmin} L={Lmin} + +Mp1 node21 noded5 node1 node1 pmos W={1*XX*Wmin} L={2*Lmin} +Mn1 node21 noded5 0 0 nmos W={1*XX*Wmin} L={2*Lmin} + +Mp2 noded5 node21 node1 node1 pmos W={2*Wmin} L={Lmin} +Mn2 noded5 node21 0 0 nmos W={1*Wmin} L={Lmin} + +Mp6 nodez node51 node1 node1 pmos W={2*XX*Wmin} L={Lmin} +Mn6 nodez node51 0 0 nmos W={1*XX*Wmin} L={Lmin} + +Mp7 node51 nodez node1 node1 pmos W={1*XX*Wmin} L={Lmin} +Mn7 node51 nodez 0 0 nmos W={1*XX*Wmin} L={Lmin} +.ends +************************************************************************************************* + +************************************************************************************************* +* DFPRQN +************************************************************************************************* +*drive strength-----------------------------------------+ +*in3----(like resest)-nodeRN-----------------------+ | +*in2 ---(like i/p)-nodeD---------------------+ | | +*in1 ---(like clk)-nodeCP-------------+ | | | +*output-------------------------+ | | | | +*vdd ---------------------+ | | | | | +*ground--------------+ | | | | | | +* | | | | | | | +* v v v v v v v +.subckt DFPRQN_SUB 0 node1 nodez nodeCP noded nodeRN XX=1 + +*REACTION + +Mn8 nodez node22 0 0 nmos W={2*XX*Wmin} L={Lmin} +Mp8 nodez node22 node1 node1 pmos W={4*XX*Wmin} L={Lmin} +Mn7 node22 nodez 0 0 nmos W={1*XX*Wmin} L={Lmin} +Mp7 node22 nodez node1 node1 pmos W={1*XX*Wmin} L={Lmin} +Mn2 1 node21 0 0 nmos W={2*XX*Wmin} L={Lmin} +Mp2 1 node21 node1 node1 pmos W={4*XX*Wmin} L={Lmin} +Mn1 node21 1 0 0 nmos W={1*XX*Wmin} L={2*Lmin} +Mp1 node21 1 node1 node1 pmos W={1*XX*Wmin} L={2*Lmin} + +*TRANSMISSION GATE +Mp41 noded nodeCP node21 node1 pmos W={2*XX*Wmin} L={Lmin} +Mn4 noded nodeCPN node21 0 nmos W={2*XX*Wmin} L={Lmin} +Mn5 2 nodeCP node22 0 nmos W={2*XX*Wmin} L={Lmin} +Mp51 2 nodeCPN node22 node1 pmos W={2*XX*Wmin} L={Lmin} +*RESET +Mn21 3 nodeRN 0 0 nmos W={4*XX*Wmin} L={Lmin} +Mn20 2 1 3 0 nmos W={4*XX*Wmin} L={Lmin} +Mp12 node22 nodeRN node1 node1 pmos W={2*XX*Wmin} L={Lmin} +Mp11 2 nodeRN node1 node1 pmos W={4*XX*Wmin} L={Lmin} +Mp10 2 1 node1 node1 pmos W={4*XX*Wmin} L={Lmin} +* +Mn3 nodeCPN nodeCP 0 0 nmos W={1*XX*Wmin} L={Lmin} +Mp3 nodeCPN nodeCP node1 node1 pmos W={2*XX*Wmin} L={Lmin} + +.ends +************************************************************************************************ + +************************************************************************************************ +* DFPHQ +************************************************************************************************ +*drive strength-----------------------------------------+ +*in3----(like i/p)-nodeD---------------------------+ | +*in2 ---(like clk)-nodeCP--------------------+ | | +*in1 ---(like enable)-nodeE-----------+ | | | +*output-------------------------+ | | | | +*vdd ---------------------+ | | | | | +*ground--------------+ | | | | | | +* | | | | | | | +* v v v v v v v +.subckt DFPHQ_SUB 0 node1 nodeZ nodeE nodeCP nodeD XX=1 + +Mn6 nodeD nodeEN 1 0 nmos W={3*XX*Wmin} L={Lmin} +Mp9 nodeEN nodeE node1 node1 pmos W={2*XX*Wmin} L={Lmin} +Mn5 noded2 nodeCP node22 0 nmos W={2*XX*Wmin} L={Lmin} +Mp41 1 nodeCP node21 node1 pmos W={3*XX*Wmin} L={Lmin} +Mp8 nodeZ node22 node1 node1 pmos W={4*XX*Wmin} L={Lmin} +Mn4 1 nodeCPN node21 0 nmos W={3*XX*Wmin} L={Lmin} +Mp7 node22 nodeZ node1 node1 pmos W={1*XX*Wmin} L={Lmin} +Mn3 nodeCPN nodeCP 0 0 nmos W={1*XX*Wmin} L={Lmin} +Mp51 noded2 nodeCPN node22 node1 pmos W={2*XX*Wmin} L={Lmin} +Mn2 noded2 node21 0 0 nmos W={2*XX*Wmin} L={Lmin} +Mn1 node21 noded2 0 0 nmos W={1*XX*Wmin} L={2*Lmin} +Mp61 nodeD nodeE 1 node1 pmos W={3*XX*Wmin} L={Lmin} +Mp3 nodeCPN nodeCP node1 node1 pmos W={2*XX*Wmin} L={Lmin} +Mn9 nodeEN nodeE 0 0 nmos W={1*XX*Wmin} L={Lmin} +Mp2 noded2 node21 node1 node1 pmos W={4*XX*Wmin} L={Lmin} +Mn8 nodeZ node22 0 0 nmos W={2*XX*Wmin} L={Lmin} +Mp1 node21 noded2 node1 node1 pmos W={1*XX*Wmin} L={2*Lmin} +Mn7 node22 nodeZ 0 0 nmos W={1*XX*Wmin} L={Lmin} + +.ends +************************************************************************************************ + +************************************************************************************************ +* Full Adder +************************************************************************************************ +*drive strength------------------------------------------------+ +*in3---------------------------nodeA--------------------+ | +*in2 --------------------nodeB---------------------+ | | +*in1 -------------nodeC----------------------+ | | | +*output2-(Carry)----------------------+ | | | | +*output1-(sum)------------------+ | | | | | +*vdd ---------------------+ | | | | | | +*ground--------------+ | | | | | | | +* | | | | | | | | +* v v v v v v v v +.subckt FA_SUB 0 node1 nodeSo nodeCo nodeC nodeB nodeA XX=1 + +Mn1 nodecon nodea node4 0 nmos W={2*XX*Wmin} L={Lmin} +Mp1 1 nodea node1 node1 pmos W={4*XX*Wmin} L={Lmin} + +Mn2 node4 nodeb 0 0 nmos W={2*XX*Wmin} L={Lmin} +Mp2 1 nodeb node1 node1 pmos W={4*XX*Wmin} L={Lmin} + + +Mn3 5 nodea 0 0 nmos W={2*XX*Wmin} L={Lmin} + +Mp3 4 nodeb node1 node1 pmos W={4*XX*Wmin} L={Lmin} +Mp4 nodecon nodea 4 node1 pmos W={4*XX*Wmin} L={Lmin} + +Mn4 5 nodeb 0 0 nmos W={2*XX*Wmin} L={Lmin} + +Mp5 nodecon nodec 1 node1 pmos W={4*XX*Wmin} L={Lmin} +Mn5 nodecon nodec 5 0 nmos W={2*XX*Wmin} L={Lmin} + +Mp6 2 nodea node1 node1 pmos W={4*XX*Wmin} L={Lmin} + +Mn6 3 nodea 0 0 nmos W={2*XX*Wmin} L={Lmin} +Mp7 2 nodeb node1 node1 pmos W={4*XX*Wmin} L={Lmin} + +Mn7 3 nodeb 0 0 nmos W={2*XX*Wmin} L={Lmin} + +Mp8 2 nodec node1 node1 pmos W={4*XX*Wmin} L={Lmin} + +Mn8 3 nodec 0 0 nmos W={2*XX*Wmin} L={Lmin} + +Mp9 nodeson nodecon 2 node1 pmos W={4*XX*Wmin} L={Lmin} + +Mn9 nodeson nodecon 3 0 nmos W={2*XX*Wmin} L={Lmin} + +Mp10 9 nodea node1 node1 pmos W={6*XX*Wmin} L={Lmin} +Mn10 7 nodea 0 0 nmos W={3*XX*Wmin} L={Lmin} +Mp11 8 nodeb 9 node1 pmos W={6*XX*Wmin} L={Lmin} + +Mn11 6 nodeb 7 0 nmos W={3*XX*Wmin} L={Lmin} +Mp12 nodeSon nodec 8 node1 pmos W={6*XX*Wmin} L={Lmin} + +Mn12 nodeSon nodec 6 0 nmos W={3*XX*Wmin} L={Lmin} + +Mp13 nodeCo nodecon node1 node1 pmos W={4*XX*Wmin} L={Lmin} +Mn13 nodeCo nodecon 0 0 nmos W={2*XX*Wmin} L={Lmin} + +Mp14 nodeSo nodeSon node1 node1 pmos W={4*XX*Wmin} L={Lmin} + +Mn14 nodeSo nodeSon 0 0 nmos W={2*XX*Wmin} L={Lmin} +.ends +