diff --git a/test_cases/test-bsimcmg/inverter_ro.sp b/test_cases/test-bsimcmg/inverter_ro.sp new file mode 100644 index 000000000..544a3ffbe --- /dev/null +++ b/test_cases/test-bsimcmg/inverter_ro.sp @@ -0,0 +1,38 @@ +*Sample netlist for BSIM-CMG + +*Ring Oscillator + +.include Modelcards/modelcard.nmos +.include Modelcards/modelcard.pmos + +* --- Voltage Sources --- +vdd supply 0 dc=1.0 +Vss ss 0 0 + +* --- Inverter Subcircuit --- +.subckt mg_inv vin vout vdd gnd +NP1 vout vin vdd vdd BSIMCMG_osdi_P +NN1 vout vin gnd gnd BSIMCMG_osdi_N +.ends + +* --- Inverter --- +Xinv1 vi 1 supply ss mg_inv +Xinv2 1 2 supply ss mg_inv +Xinv3 2 3 supply ss mg_inv +Xinv4 3 4 supply ss mg_inv +Xinv5 4 vi supply ss mg_inv + +Xinv6 vi vo supply 0 mg_inv + +* --- Transient Analysis --- +.tran 0.5p 5n + +.control +pre_osdi test_osdi_win/bsimcmg.osdi +set xbrushwidth=3 +run +plot v(vo) +plot i(vss) i(vdd) +.endc + +.end diff --git a/test_cases/test-bsimcmg/inverter_transient.sp b/test_cases/test-bsimcmg/inverter_transient.sp new file mode 100644 index 000000000..e943b9dca --- /dev/null +++ b/test_cases/test-bsimcmg/inverter_transient.sp @@ -0,0 +1,36 @@ +*Sample netlist for BSIM-CMG +* (exec-spice "ngspice %s" t) +*Inverter Transient + +.include Modelcards/modelcard.nmos +.include Modelcards/modelcard.pmos +* --- Voltage Sources --- +vdd supply 0 dc=1.0 +vsig vi 0 dc=0.5 sin (0.5 0.5 1MEG) + +* --- Inverter Subcircuit --- +.subckt mg_inv vin vout vdd gnd +NP1 vout vin vdd vdd BSIMCMG_osdi_P +NN1 vout vin gnd gnd BSIMCMG_osdi_N +.ends + +* --- Inverter --- +Xinv1 vi 1 supply 0 mg_inv +Xinv2 1 2 supply 0 mg_inv +Xinv3 2 3 supply 0 mg_inv +Xinv4 3 4 supply 0 mg_inv +Xinv5 4 vo supply 0 mg_inv + +* --- Transient Analysis --- +.tran 20n 5u + +.print tran v(vi) v(vo) + +.control +pre_osdi test_osdi_win/bsimcmg.osdi +set xbrushwidth=3 +run +plot v(vi) v(vo) +.endc + +.end diff --git a/test_cases/test-bsimcmg/netlist_nmos.sp b/test_cases/test-bsimcmg/netlist_nmos.sp new file mode 100644 index 000000000..bc0d7c02d --- /dev/null +++ b/test_cases/test-bsimcmg/netlist_nmos.sp @@ -0,0 +1,28 @@ +OSDI BSIMCMG Test +*.options abstol=1e-15 + +* one voltage source per MOS terminal: +VD dd 0 1 +VG gg 0 1 +VS ss 0 0 +VB bb 0 0 + +* model definitions: +*.model bsim4_osdi bsim4va +.include Modelcards/modelcard.nmos + +*OSDI BSIM4: +* Where to put instance parameters channel width and length? +N1 dd gg ss bb BSIMCMG_osdi_N ; W=5u L=0.2u + +.control +pre_osdi test_osdi_win/bsimcmg.osdi +set xbrushwidth=3 +* a DC sweep: drain, gate +dc Vd 0 2.5 0.01 VG 0 2.5 0.5 +* plot source current +plot i(VS) + +.endc + +.end diff --git a/test_cases/test-bsimcmg/netlist_pmos.sp b/test_cases/test-bsimcmg/netlist_pmos.sp new file mode 100644 index 000000000..b56010fa8 --- /dev/null +++ b/test_cases/test-bsimcmg/netlist_pmos.sp @@ -0,0 +1,28 @@ +OSDI BSIMCMG Test +*.options abstol=1e-15 + +* one voltage source per MOS terminal: +VD dd 0 -1 +VG gg 0 -1 +VS ss 0 0 +VB bb 0 0 + +* model definitions: +* +.include Modelcards/modelcard.pmos + +*OSDI BSIMCMG: +* Where to put instance parameters channel width and length? +N1 dd gg ss bb BSIMCMG_osdi_P + +.control +pre_osdi test_osdi_win/bsimcmg.osdi +set xbrushwidth=3 +* a DC sweep: drain, gate +dc Vd 0 -1.8 -0.01 VG 0 -1.8 -0.3 +* plot source current +plot i(VS) + +.endc + +.end diff --git a/test_cases/test-bsimcmg/noise.sp b/test_cases/test-bsimcmg/noise.sp new file mode 100644 index 000000000..e7cc7ad31 --- /dev/null +++ b/test_cases/test-bsimcmg/noise.sp @@ -0,0 +1,47 @@ +*Samle netlist for BSIM-MG +* (exec-spice "ngspice %s" t) +* Drain Noise Simulation + +.option abstol=1e-6 reltol=1e-6 post ingold +.temp 27 + +*.hdl "bsimcmg.va" +.include Modelcards/modelcard.nmos + +* --- Voltage Sources --- +vds 1 0 dc=1v +vgs gate 0 dc=0.5v ac=1 +vbs bulk 0 dc=0v + +* --- Circuit --- +lbias 1 drain 1m +cload drain 2 1m +rload 2 0 R=1 noise=0 +NM1 drain gate 0 bulk 0 BSIMCMG_osdi_N TFIN=15n L=30n NFIN=10 NRS=1 NRD=1 ++ FPITCH = 4.00E-08 + +* --- Analysis --- +*.op +**.dc vgs -0.5 1.5 0.01 +**.print dc i(lbias) +*.ac dec 11 1k 100g +*.noise v(drain) vgs 1 +**.print ac i(cload) +*.print ac v(drain) +*.print noise inoise onoise + +.control +pre_osdi test_osdi_win/bsimcmg.osdi +op + +ac dec 11 1k 100g +plot vdb(drain) + +noise v(drain) vgs dec 11 1k 100g +print all +echo "silence in the studio, no noise today" + +.endc + +.end + diff --git a/test_cases/test-bsimcmg/ringosc_17stg.sp b/test_cases/test-bsimcmg/ringosc_17stg.sp new file mode 100644 index 000000000..4677d8292 --- /dev/null +++ b/test_cases/test-bsimcmg/ringosc_17stg.sp @@ -0,0 +1,54 @@ +*Sample netlist for BSIM-MG +* (exec-spice "ngspice %s" t) +*17-stage ring oscillator + +.include Modelcards/modelcard.nmos +.include Modelcards/modelcard.pmos + +* --- Voltage Sources --- +vdd supply 0 dc=1.0 + +* --- Inverter Subcircuit --- +.subckt mg_inv vin vout vdd gnd +NP1 vout vin vdd vdd BSIMCMG_osdi_P +NN1 vout vin gnd gnd BSIMCMG_osdi_N +.ends + +* --- 17 Stage Ring oscillator --- +Xinv1 1 2 supply 0 mg_inv +Xinv2 2 3 supply 0 mg_inv +Xinv3 3 4 supply 0 mg_inv +Xinv4 4 5 supply 0 mg_inv +Xinv5 5 6 supply 0 mg_inv +Xinv6 6 7 supply 0 mg_inv +Xinv7 7 8 supply 0 mg_inv +Xinv8 8 9 supply 0 mg_inv +Xinv9 9 10 supply 0 mg_inv +Xinv10 10 11 supply 0 mg_inv +Xinv11 11 12 supply 0 mg_inv +Xinv12 12 13 supply 0 mg_inv +Xinv13 13 14 supply 0 mg_inv +Xinv14 14 15 supply 0 mg_inv +Xinv15 15 16 supply 0 mg_inv +Xinv16 16 17 supply 0 mg_inv +Xinv17 17 1 supply 0 mg_inv + +* --- Initial Condition --- +.ic v(1)=1 + +.tran 1p 1n + +.measure tran t1 when v(1)=0.5 cross=1 +.measure tran t2 when v(1)=0.5 cross=7 +.measure tran period param='(t2-t1)/3' +.measure tran frequency param='3/(t2-t1)' +.measure tran delay_per_stage param='period/34' + +.control +pre_osdi test_osdi_win/bsimcmg.osdi +set xbrushwidth=3 +run +plot v(1) +.endc + +.end diff --git a/test_cases/test-bsimcmg/simple_inverter_dc.sp b/test_cases/test-bsimcmg/simple_inverter_dc.sp new file mode 100644 index 000000000..b47b7514f --- /dev/null +++ b/test_cases/test-bsimcmg/simple_inverter_dc.sp @@ -0,0 +1,27 @@ +*Sample netlist for BSIM-CMG +* (exec-spice "ngspice %s" t) +*Inverter DC + +.include Modelcards/modelcard.nmos +.include Modelcards/modelcard.pmos +* --- Voltage Sources --- +vdd supply 0 dc=1.0 +vsig vin 0 dc=0.5 sin (0.5 0.5 1MEG) + +NP1 vout vin supply supply BSIMCMG_osdi_P +NN1 vout vin 0 0 BSIMCMG_osdi_N + +* --- DC Analysis --- +*.dc vsig 0 1 0.01 + +* --- Transient Analysis --- +.tran 10n 2u + +.control +pre_osdi test_osdi_win/bsimcmg.osdi +set xbrushwidth=3 +run +plot v(vout) v(vin) +.endc + +.end