38 lines
825 B
VHDL
38 lines
825 B
VHDL
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-- Very simple logic for PWM waveform generation.
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.math_real.all;
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entity pwm is
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port ( output : out std_logic := '1');
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end pwm;
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architecture pwm_impl of pwm is
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constant Cycles : Integer := 1000;
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constant Samples : Integer := 1000;
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constant uSec : Time := 1 us;
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begin
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process
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variable j : Integer := 0;
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variable width : Integer := Cycles / 2;
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variable sine : Real;
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begin
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wait for width * uSec;
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output <= '0';
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wait for (Cycles - width) * uSec;
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j := j + 1;
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if j = Samples then
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j := 0;
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end if;
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sine := sin(real(j) * MATH_2_PI / real(Samples));
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width := integer(real(Samples) * (1.0 + sine) / 2.0);
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if width = 0 then
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output <= '0';
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else
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output <= '1';
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end if;
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end process;
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end pwm_impl;
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