myrtle 2a84cc9c55 xilinx: Add LUT route-thru pips (#1703) ... Signed-off-by: gatecat <gatecat@ds0.me>		2026-04-20 11:47:38 +02:00
..
filters.py	xilinx: Better use global clocking resources	2026-04-09 13:37:52 +02:00
parse_sdf.py	xilinx: Import timings for BRAM (#1653)	2026-03-02 10:10:55 +01:00
tileconn.py	himbaechel: Adding a xilinx uarch for xc7 with prjxray	2023-11-14 17:12:09 +01:00
xilinx_device.py	himbaechel: Adding a xilinx uarch for xc7 with prjxray	2023-11-14 17:12:09 +01:00
xilinx_gen.py	xilinx: Add LUT route-thru pips (#1703)	2026-04-20 11:47:38 +02:00