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187 Commits

Author SHA1 Message Date
Sylvain Munaut 9dd68aa0e2 ice40: Take placed SB_GBs into account when placing PLLs 
Because the PLLs drive global networks, we need to account for
already existing and placed SB_GBs when trying to place/pack them.

Theses can be user instanciated SB_GBs with BEL attribute, or
SB_GB_IOs that got converted during the IO packing.

This patch assumes that:
 - If a PLL is used the output A global network is always used, even
   if there is no connection to the global output pin
 - If a PLL with a singe output is used, then the B output global
   network is still free to be used by whatever.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2019-04-16 10:12:28 +02:00
Sylvain Munaut 6cb4e2e83b ice40/pack: During IO packing, remove any unused input connection 
This is mostly for the benefit of PLL placement because the D_IN_x
ports are used for other purposes when PLL is enabled so we need to
make sure nothing is connected there already. (even an unused net is
too much)

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2019-04-11 13:52:23 +02:00
David Shah d27ec2cd15 ice40: Don't constrain to a PLL bel that has already been used 
Fixes #258

Signed-off-by: David Shah <dave@ds0.me>
 2019-04-01 12:25:32 +01:00
Sylvain Munaut d401e3e1a0 ice40: Add support for SB_I2C and SB_SPI 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2019-03-25 23:48:59 +01:00
David Shah 054be887ae ice40: PLLs can't conflict with themselves 
Fixes error building testcase from #145

Signed-off-by: David Shah <dave@ds0.me>
 2019-02-09 19:27:52 +00:00
David Shah 170bf8a5ec ice40: Don't create PLLOUT_B buffer for single-output PLL variants 
Signed-off-by: David Shah <dave@ds0.me>
 2019-02-09 10:41:22 +00:00
David Shah 265fa1be16
Merge pull request #211 from smunaut/ice40_ram_attrs 
ice40/pack: Copy attributes to packed cell
 2019-01-21 11:10:38 +00:00
Sylvain Munaut b274a8f8f0 ice40/pack: Copy attributes to packed RAM cells 
Useful to allow manual placement of SPRAM/EBR using BEL attribute
for instance

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2019-01-19 15:49:21 +01:00
Sylvain Munaut 830d462f92 ice40: Add error message if a selected site is not Global Buffer capable 
... rather than assert()-out during the call to getWireBelPins() call

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2019-01-18 17:53:24 +01:00
David Shah 4444a39fd4 ice40: Improve handling of unconstrained IO 
Signed-off-by: David Shah <dave@ds0.me>
 2018-12-26 16:00:19 +00:00
David Shah 75335d4e1a ice40: Fix LOCK feedthrough insertion with carry or >8 LUTs 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-12-20 18:50:34 +00:00
David Shah 144363693d ice40: Report error for unsupported PLL FEEDBACK_PATH values 
Signed-off-by: David Shah <dave@ds0.me>
 2018-12-06 11:29:33 +00:00
whitequark 7fad6058bd ice40: add reset global promotion threshold. 2018-12-04 07:40:55 +00:00
Daniel Serpell d4b3c1d819 ice40: Add support for placing SB_LEDDA_IP block. 
Signed-off-by: Daniel Serpell <daniel.serpell@gmail.com>
 2018-12-01 22:27:04 -03:00
David Shah 8af367ad0a ice40: Add a warning for unconstrained IO 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-29 19:35:19 +00:00
David Shah fc08856537
Merge pull request #157 from whitequark/fanout-thresh 
ice40: raise CE global promotion threshold
 2018-11-29 09:12:47 +00:00
whitequark db96b88d79 ice40: raise CE global promotion threshold. 2018-11-29 00:12:48 +00:00
whitequark a974124a7a ice40: print fanout of nets promoted to globals. 2018-11-28 23:52:48 +00:00
Sylvain Munaut ba958d1792 ice40: Try to be helpful and suggest using PAD PLL instead of CORE 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-28 16:04:58 +01:00
Sylvain Munaut a65b12e8d6 ice40: Revamp the whole PLL placement/validity check logic 
We do a pre-pass on all the PLLs to place them before packing.

To place them:
 - First pass with all the PADs PLLs since those can only fit at one
   specific BEL depending on the input connection
 - Second pass with all the dual outputs CORE PLLs. Those can go
   anywhere where there is no conflicts with their A & B outputs and
   used IO pins
 - Third pass with the single output CORE PLLs. Those have the least
   constrains.

 During theses passes, we also check the validity of all their connections.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-28 16:04:43 +01:00
David Shah 80f7ef4b4b ice40: Finer-grained control of global promotion 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-27 19:06:55 +00:00
Sylvain Munaut 584e8c58a6 ice40: During global promotion, only promote if this will actually fit ! 
We need to take into account the global networks that are already used
and possibly locked to know what we can promote since all networks
can't drive resets / clock-enables

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-26 12:51:14 +01:00
David Shah 2951e37b45 ice40: Fix disconnection of PACKAGEPIN for PAD PLLs 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-24 17:49:26 +00:00
Sylvain Munaut 9c5f4fb885 ice40/pll: Fix typo when testing for global port output net 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-20 23:53:08 +01:00
Sylvain Munaut e8556aff37 ice40: Add support for SB_RGBA_DRV 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut de8de6304f ice40: Add global network output support for LFOSC/HFOSC 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut 271cc7be11 ice40/pack: Add helper to constain cells that are unique in the FPGA 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut 519d4e2af8 ice40: Add support for SB_GB_IO 
During packing we replace them by standard SB_IO cells and create the
'fake' SB_GB that matches that IO site global buffer connection.

It's done in a separate pass because we need to make sure the nextpnr iob
have been dealt first so we have our final Bel location on the SB_IO.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut d8e4c21d96 ice40: Add support for PLL global outputs via PADIN 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut bc9f2da470 ice40: Introduce the concept of forPadIn SB_GB 
Those are cells that are created mainly to handle the various sources a
global network can be driven from other than a user net.

When the flag is set, this means the global network usually driven by
this BEL is in fact driven by something else and so that SB_GB BEL and
matching global network can't be used.

This is also what gets used to set the extra bits during bitstream
generation.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut ad23caef33 ice40/pll: Add proper support for PLLOUT_SELECT_xxx attributes 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut 35e9ec7737 ice40: Minor fix in predicate checking for logic port 
- is_sb_pll40 covers all the PLL types
 - Use helper to test for gbuf

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut ac5d767d4f ice40/pack: Stop looking for BEL when we have one during PLL placement 
Ideally we should first process all the PLL that are constrained somehow
(either explicitely or because they are PAD) and then free place the rest.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut 5fb3353557 ice40/pack: Allow PLL to be constrained via 'BEL' attributes 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut 8c69a3bba3 ice40/pack: Make sure we don't use a LOCKED bel when placing PLL 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-19 18:20:20 +01:00
Sylvain Munaut e1e8d8cd14 ice40: Add warning if an instanciated SB_IO has its PACKAGE_PIN used elsewhere 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-16 16:36:57 +01:00
David Shah fc5e6bec9a timing: Add support for clock constraints 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-12 14:03:58 +00:00
David Shah 122771cac3 timing: iCE40 Arch API changes for clocking info 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-12 14:03:58 +00:00
Clifford Wolf b4dc6b8845 Add info message for promoted global nets 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-10-03 13:40:21 +02:00
David Shah 7ef8a7415d ice40: Add error for bad PACKAGE_PIN connections 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-10-03 12:14:49 +01:00
David Shah ea03aafc26 clangformat 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-09-30 15:13:18 +01:00
Clifford Wolf 07cf349ee4
Merge pull request #79 from YosysHQ/ice40lvds 
ice40: Adding LVDS input support
 2018-09-25 18:21:56 +02:00
Clifford Wolf 1eb7411fb0
Merge pull request #76 from YosysHQ/plloutglobal_fix 
Add needed PLLOUTGLOBAL ports and mapped it
 2018-09-25 18:15:00 +02:00
David Shah f1aa7093fe ice40: Fix carry packer bug 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-09-25 15:52:32 +01:00
David Shah 2ee86ab5a8 ice40: Tristate IO support fixes 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-09-24 15:25:37 +01:00
Miodrag Milanovic f8e258825f Added required checks for PLL and fixed messages eol 2018-09-19 18:41:28 +02:00
Miodrag Milanovic fdf7593c42 Add needed PLLOUTGLOBAL ports and mapped it properly 2018-09-12 18:33:08 +02:00
Sergiusz Bazanski 1bf22a7f64 ice40: make PLL packing more robust 2018-08-19 21:30:55 +01:00
Clifford Wolf e03ae50e21 Get rid of PortPin and BelType (ice40, generic, docs) 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-08 17:01:18 +02:00
David Shah fd2174149c Fixing constraint placement bugs 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-03 16:29:44 +02:00
David Shah 7e9209878c Reworking packer and placer to use new generic rel legaliser 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-03 15:00:32 +02:00
David Shah 483f1b772c ice40: Promote 'logic' globals as well as clock/enable/reset 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-03 09:56:56 +02:00
David Shah 0414c93403 ice40: Add HFOSC support, force fabric routing on oscillators for now 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-08-01 09:45:08 +02:00
Sergiusz Bazanski 85fc356fc1 clangformat 2018-08-01 03:59:27 +01:00
Eddie Hung 950f33c1bb clangformat 2018-07-25 17:53:01 -07:00
Sergiusz Bazanski db4f2d2318 ice40: check PLL PACKAGEPIN drives only PLL, cosmetics 2018-07-25 11:47:24 +01:00
Sergiusz Bazanski c554ab1ef0 clang-format 2018-07-25 11:32:40 +01:00
Sergiusz Bazanski aad0d3eb35 ice40: support PLL40_*_PAD, fix pass-through LUT for LOCK 2018-07-25 11:32:21 +01:00
Sergiusz Bazanski 2039112a47 ice40: after review 2018-07-24 15:59:18 +01:00
Sergiusz Bazanski b31e95f82c Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnr into q3k/pll 2018-07-24 15:54:03 +01:00
David Shah 5a170f286c ice40: Remove use of deprecated APIs 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-24 15:52:56 +02:00
David Shah 4359197dfe ice40: Trim BRAM constant inputs, reduces routing congestion around BRAM 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-24 11:21:10 +02:00
Sergiusz Bazanski 90ba958abe ice40: fixes before review 2018-07-24 03:19:22 +01:00
Sergiusz Bazanski fae7994bc3 clang-format 2018-07-24 02:55:40 +01:00
Sergiusz Bazanski 065ea95eab ice40: Move spliceLUT back to pack.cc 2018-07-24 02:55:40 +01:00
Sergiusz Bazanski e6c7b14465 ice40: Refactor PLL/LOCK LUT splicing out into Arch:: 2018-07-24 02:55:40 +01:00
Sergiusz Bazanski 69233385f8 ice40: Emit feed-through LUTs for PLL/LOCK 2018-07-24 02:55:40 +01:00
Sergiusz Bazanski db31c0625b ice40: Fail early on SB_PLL40_*_PAD cells 2018-07-24 02:55:38 +01:00
Sergiusz Bazanski 2b1f7875bb ice40: Implement emitting PLLs 2018-07-24 02:38:10 +01:00
David Shah 79dc910b40 ice40: Trim DSP inputs that are constant where appropriate 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-19 14:32:30 +02:00
David Shah bff7d673ed ice40: Packer and bitstream gen support for MAC16s 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-19 14:03:48 +02:00
David Shah 08ceb8a059 ice40: Renaming 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-18 14:34:32 +02:00
David Shah ddd94edfe0 ice40: Fixes for inverted clocks 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-18 14:01:19 +02:00
David Shah 70cfa7a6a4 ice40: Make assignArchArgs a Arch method; call also after legaliser 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-18 12:21:02 +02:00
David Shah c75a924c3f ice40: Assign ArchArgs after packing 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-18 12:12:05 +02:00
Clifford Wolf c05bea12e0 Add ctx->pack() API 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-07-13 15:16:44 +02:00
Miodrag Milanovic 1cf8293019 Fixed macros and includes for MSVC 2018-07-03 08:53:44 +02:00
David Shah 302ccc14cf ice40: UltraPlus SPRAM working 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-06-29 19:58:08 +02:00
David Shah 3b90f3698f ice40: Fix carry packing in some degenerate cases 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-06-29 15:10:29 +02:00
David Shah c0724a7e97 ice40: Only pack up to one SB_CARRY into a LC 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-06-27 16:24:44 +02:00
David Shah 28e851cf45 ice40: Fix IO packer 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-06-27 16:16:38 +02:00
David Shah 885fe93a17 ice40: Carry packer bugfix 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-06-27 15:24:34 +02:00
David Shah 998ab2b20a ice40: Fixing the carry packer for a larger design 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-06-27 12:43:29 +02:00
David Shah 09c0d96105 ice40: Fixing packing of CIN constant drivers 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-06-26 20:02:19 +02:00
David Shah 21d5a04501 Carry chains now routable 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-06-26 15:55:50 +02:00
David Shah 6f12f2b7e8 Working on debugging the carry legaliser 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-06-26 15:06:59 +02:00
David Shah 29df577f14 Fixing packing of carry cells 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-06-26 14:37:01 +02:00
David Shah ded9df61dc Working on debugging carry packer 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-06-26 13:08:28 +02:00
Miodrag Milanovic db890d3a81 nets and cells are unique_ptr's 2018-06-25 21:33:48 +02:00
David Shah 64208da1f9 ice40: Remove constant driver cells in packer 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-06-25 16:29:37 +02:00
Miodrag Milanovic a279720fc1 merge 2018-06-25 16:22:08 +02:00
Miodrag Milanovic 6de8b4ef7d some more memory leaks 2018-06-25 15:52:55 +02:00
David Shah 6d154cfa13 ice40: Creating a carry chain splitter function 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-06-25 15:39:46 +02:00
David Shah 1e8840b0f9 Update from increased clangformat line length 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-06-23 16:12:52 +02:00
David Shah 289fca0976 ice40: Move global net test to Arch 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-06-23 12:09:01 +02:00
Miodrag Milanovic cb92c10b99 Cleanup almost all deprecation warnings 2018-06-23 09:42:48 +02:00
David Shah 8850f86a8a ice40: SB_LFOSC support, fabric routing only 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-06-22 19:21:39 +02:00
Clifford Wolf aa81f9d648 Switched from clifford@clifford.at to clifford@symbioticeda.com for copyright headers 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-22 16:19:17 +02:00
David Shah 63baa10032 ice40: Make the packer deterministic 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-06-22 12:57:22 +02:00
Miodrag Milanovic 8fac26c2b7 Fixed return codes for packer, placer and router 2018-06-21 17:56:45 +02:00