* gatemate: add CCF floorplanning parser
* apply constraints
* cleanup
* print detected region and error if not found
* Add wildcard matching
* Validate placebox and use official coordinate system
* Fix some messages
* gatemate: improve mode arg error message
* gatemate: fix initial capitals and periods in log_*() messages
* gatemate: replace operation -> performance for mode in help and log_*()
This is the term used both in the datasheet and the primitive library PDF.
* gatemate: add alternate clock routes
* use additional pins
* Fix clock router and timings
* Fix DDR nets
* Test passtrough concept
* remove not used variable
* wip
* handle pip masks
* Cleanup
* create CPE_CPLINES cells and set properties on them
* Fix pip masking
* rough code to break cplines into subnets
* add ports to cell
* mux bridges need cell bel pins too
* fix multiplier output register packing
* remove empty if
* Fix ODDR
* Add options to disable some pips
* Use resources info
* mask field to resource field
* produce valid netlist with propagation netlist at least
* adapt reassign_cplines for internal resource pips
* Handle block and resources
* fix formatting
* It is required to set all mandatory properties now
* arch API for resources
* current progress
* Add option to skip bridges
* perform per-wire resource congestion costing
* Added no-cpe-cp option
* resource bugfix
* comment out spammy debug message
* Fix routing conflicts issues
* allow only some pass trough for clock router
* handle inversion bits for pass signals
* verify inversion before/after assigning bridges
* we care only if there is net
* Revert "we care only if there is net"
This reverts commit 3da2769e31.
* Revert "verify inversion before/after assigning bridges"
This reverts commit 8613ee17c8.
* chipdb version bump
* clangformat
* cleanup
* cleanup
* Initial conversion to GroupId
* Keep group info in pip extra
* Cleanup headers
* Initialize resource efficiently
* Addressing review comments
* improve resource docs
* Make CP lines not use as clocks as default
---------
Co-authored-by: Lofty <dan.ravensloft@gmail.com>
* Gowin. DSP. Implement MULT12x12.
The 5A series DSP differs from previous ones. Many things have been
greatly simplified: there are only two control signals of one type per
cell (2 CLK, 2 CE and 2 RESET), and these signals are now explicitly
specified in the DSP attributes, which makes the automatic assignment
mechanism unnecessary for them.
The DSP occupies 3 cells instead of nine due to the exclusion of 4
low-bit multipliers - now there are only two 12x12. There will naturally
be clusters, but they will be simpler and consist of other primitives.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Gowin. Implement MULTADDALU12X12.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---------
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: Update arch gen to use msgspec chipdb format
Apycula now uses msgspec MessagePack serialization instead of pickle
for the chipdb files. This change:
- Replaces pickle with msgspec via load_chipdb()
- Changes file extension from .pickle to .msgpack.gz
- Updates grid access patterns for new Device structure where
db.grid[y][x] returns ttyp (int) directly, use db[y, x] for Tile
Co-Authored-By: Claude Opus 4.5 <noreply@anthropic.com>
* Update chipdb extension to .msgpack.xz
Apicula switched from gzip to lzma compression for chipdb files.
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
---------
Co-authored-by: Claude Opus 4.5 <noreply@anthropic.com>
Only one bit per macro is responsible for the bit width of operands. We
add operand width tracking and do not allow different operands to be
combined in a single macro.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Gowin. Add GW5AST-138C chip.
The ability to perform P&R for the largest GW5A series chip currently
available has been added, which has its own characteristics:
- the need to invert pin function configuration signals - these
signals are not part of the design, but are nextpnr command line
keys for specifying the activation of alternative pin functions such as
I2C;
- some clock PIPs are encoded not by fuses, but by applying VCC/GND to
special inputs. This is also not part of the design and is not a
dynamic clock selection primitive - it is simply an addition to the
fuses.
- added check for DFF and SSRAM placement in upper slots - prior to
this chip, SSRAM was not supported and there was no need for this
check.
- since the chip is divided into two parts in terms of the global
clock network, a flag is introduced to indicate which part the wire
belongs to. This is only requested for clock wires.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Gowin. Fix style.
Use C++ type cast.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---------
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Gowin. BUGFIX. BSRAM SP separation.
The new SP cell must inherit the byte size - 8 or 9 bits.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Gowin. Byte Enables processing in SP.
Single Port with a data width of 32/36 is internally configured as Dual
Port with 16/18. Even and odd words are processed separately by ports A
and B.
With the advent of byte enable support, it became necessary to switch
these signals differently.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---------
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
The TLVDS_IBUF_ADC IO primitives have been implemented, which provide a
signal for ADC bus 2. These differential IO primitives also have an
additional input that allows them to be disabled, thereby providing
dynamic switching of the signal source for the ADC.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
ADC support for GW5A-25 chips has been added.
The inputs of this primitive are fixed and do not require routing,
although they can be switched dynamically.
The .CST file also specifies the pins used as signal sources for the
bus0 and bus1 ADC buses.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gatemate: handle default parameters for IO
This is probably a VHDL specific issue. In VHDL, there is no
black-box. Primitive instantiations are done using VHDL component
instantiations and the component must have been declared with all its
ports and parameters (generic). Currently the components are
translated from cells_sim.v and cells_bb.v
If a user doesn't override a parameter, the default value is used
instead. As a consequence, nextpnr can have 'UNDEFINED' for DRIVER
or SLEW parameters of CC_IOBUF. I think this is a main difference
with verilog, where unspecified parameters do not appear.
With this change, the UNPLACED value of PIN_NAME and UNDEFINED value
of DRIVE are simply ignored.
* gatemate/pack_io.cc: also handle UNDEFINED for id_SLEW
Since ctx->getArchArgs() no longer returns architecture-specific
arguments, we read the args field directly.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gatemate: Use GATEMATE_DIE attribute to select placement die
* add DIE parameter in CCF
* add penalty delay when crossing between dies
* Add predictDelay
In the GW5A series, the primitive SemiDual Port BSRAM cannot function
when the width of any of the ports is 32/36 bits - it is necessary to
divide one block into two identical ones, each of which will be
responsible for 16 bits.
Here, we perform such a division and, in addition, ensure that the new
cells resulting from the division undergo the same packing procedure as
the original ones.
Naturally, with some reservations (the AUX attribute is responsible for
this) - in the case of SP, when service elements are added, it makes
sense to do this immediately for 32-bit SP and only then divide.
Also, SDPs are currently being corrected for cases where both ports are
‘problematic’, but it may happen that one port is 32 and the other is,
say, 1/2/4/8/16. This has been left for the future.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
In the new series of chips, the SemiDual Port primitive has one RESET
pin instead of two in previous versions - RESETA and RESETB.
Physically, the two pins are still there and both must be connected,
with RESETA being constant.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Over time, it became clear that the special status of corner tiles is
handled in other parts of the toolchain, and in the GW5A chip series, it
began to interfere—in this series, IO can be located in the corners.
So we move the only function (creating VCC and GND) to the extra
function itself, and at the same time create a mechanism for explicitly
specifying the location of these sources in Apicula when necessary.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Check SER_CLK more
* Use connectPorts
* move rewire code
* Move data structures
* move placement decision for later
* cleanups
* find working layout
* clangformat
* Inverted input on ODDR
* Fix some tests
* Copy clocks for multi die
* cleanup
* reporting
* bugfix
* handle PLL special inputs
* Fix user globals
* Proper DDR per bank and cleanup
* Add extra data for die regions and create them
* Better forced_die implementation
* Copy region to newly generated cells, and update when constrained
* Update PLL error messages
* Add TODO comment
* convert nodes to pips
* add plane info for node pips
* a few multiplier router fixes
* do not need node delay
* add pip delays
* cleanup
* tried fixing clock router
* add PLL delays
* fix clock routing
* Do not use actual pip delay, determine best by number of passed pips
* optimize
* proper parameter check
* more multiplier fixes
* another mult fix
* another multiplier fix
* another multiplier fix
* another multiplier fix
* another multiplier fix
* another multiplier fix
* another multiplier fix
* another multiplier fix
* another multiplier fix
* another multiplier fix
* another multiplier fix
* another multiplier fix
* another multiplier fix
* another multiplier fix
* another multiplier fix
* another multiplier fix
* another multiplier fix
* another multiplier fix
* another multiplier fix
* another multiplier fix
* another multiplier fix
* log number of clock net users
* Revert "Do not use actual pip delay, determine best by number of passed pips"
This reverts commit c66e422dd0.
We want to guarantee minimum clock skew, so we need pip delay.
* route clocks from source to sink
* add time spent to route_clock
* weakly-bind non-global clocks
* clangformat
* remove dead code
* Require version 1.8
* change to assert
* add revisits in clock router
---------
Co-authored-by: Lofty <dan.ravensloft@gmail.com>
gatecat
Miodrag Milanović
mrcmry
YRabbit
Pepijn de Vos
Patrick Urban
Lofty
tgingold
Gwenhael Goavec-Merou