9 Commits

Author	SHA1	Message	Date
rowanG077	240f89081f	Add back error/warning for combinational loops	2023-08-18 09:15:37 +02:00
rowanG077	d2a489d5e9	Remove old timing analyser	2023-08-18 09:15:37 +02:00
rowanG077	596873c302	tmg: Add net_timings, crit path and slack hist	2023-08-18 09:15:37 +02:00
rowanG077	8b51674a6b	Add critical path report to modern timing engine	2023-08-18 09:15:37 +02:00
rowanG077	914999673c	Rip out budgets	2023-06-20 10:57:10 +02:00
Rowan Goemans	5b958c4d80	Analyse async paths in TimingAnalyser (#1171)	2023-06-09 08:01:47 +02:00
Maciej Kurc	9000c41c4b	Added the --ignore-rel-clk option to control timing checks for cross-domain paths, formatted code ... Signed-off-by: Maciej Kurc <mkurc@antmicro.com>	2022-09-20 14:40:40 +02:00
Maciej Kurc	9a61ad9234	Augmented TimingAnalyser class with detection of clock to clock relations ... Signed-off-by: Maciej Kurc <mkurc@antmicro.com>	2022-08-30 17:30:58 +02:00
gatecat	49f178ed94	Split up common into kernel,place,route ... Signed-off-by: gatecat <gatecat@ds0.me>	2022-04-08 13:42:54 +01:00