diff --git a/himbaechel/uarch/gatemate/constids.inc b/himbaechel/uarch/gatemate/constids.inc
index c8a484a6..34062954 100644
--- a/himbaechel/uarch/gatemate/constids.inc
+++ b/himbaechel/uarch/gatemate/constids.inc
@@ -906,14 +906,18 @@ X(USR_RSTN)
 // hardware primitive CPE_LT_U
 X(CPE_LT_U)
 // CPE_LT_U pins
-X(IN1)
-X(IN2)
-X(IN3)
-X(IN4)
+X(D0_00)
+X(D1_00)
+X(D0_01)
+X(D1_01)
+X(D0_10)
+X(D1_10)
+X(M1)
+X(M2)
+X(M3)
+X(M4)
 X(OUT)
 X(CPOUT)
-X(PINY1)
-X(CINX)
 
 // hardware primitive CPE_FF_U
 X(CPE_FF_U)
@@ -935,25 +939,19 @@ X(RAM_O)
 // hardware primitive CPE_LT_L
 X(CPE_LT_L)
 // CPE_LT_L pins
-//X(IN1)
-//X(IN2)
-//X(IN3)
-//X(IN4)
+//X(D0_00)
+//X(D1_00)
+//X(D0_01)
+//X(D1_01)
+//X(D0_10)
+//X(D1_10)
 X(COMBIN)
+//X(M1)
+//X(M2)
+//X(M3)
+//X(M4)
 //X(OUT)
 //X(CPOUT)
-//X(CINX)
-X(PINX)
-X(CINY1)
-//X(PINY1)
-X(CINY2)
-X(PINY2)
-X(COUTX)
-X(POUTX)
-X(COUTY1)
-X(POUTY1)
-X(COUTY2)
-X(POUTY2)
 
 // hardware primitive CPE_FF_L
 X(CPE_FF_L)
@@ -975,10 +973,10 @@ X(CPE_RAMIO_L)
 // hardware primitive CPE_BRIDGE
 X(CPE_BRIDGE)
 // CPE_BRIDGE pins
-//X(IN1)
-//X(IN2)
-//X(IN3)
-//X(IN4)
+X(IN1)
+X(IN2)
+X(IN3)
+X(IN4)
 X(IN5)
 X(IN6)
 X(IN7)
@@ -1001,18 +999,18 @@ X(OUT2)
 X(CPOUT1)
 X(CPOUT2)
 //X(MUXOUT)
-//X(CINX)
-//X(PINX)
-//X(CINY1)
-//X(PINY1)
-//X(CINY2)
-//X(PINY2)
-//X(COUTX)
-//X(POUTX)
-//X(COUTY1)
-//X(POUTY1)
-//X(COUTY2)
-//X(POUTY2)
+X(CINX)
+X(PINX)
+X(CINY1)
+X(PINY1)
+X(CINY2)
+X(PINY2)
+X(COUTX)
+X(POUTX)
+X(COUTY1)
+X(POUTY1)
+X(COUTY2)
+X(POUTY2)
 //X(CLK)
 //X(EN)
 //X(SR)
diff --git a/himbaechel/uarch/gatemate/pack.cc b/himbaechel/uarch/gatemate/pack.cc
index f7c61375..006f0362 100644
--- a/himbaechel/uarch/gatemate/pack.cc
+++ b/himbaechel/uarch/gatemate/pack.cc
@@ -308,6 +308,12 @@ void GateMatePacker::repack_cpe()
             if (l.z == CPE_LT_L_Z) {
                 if (!cell.second->params.count(id_INIT_L20))
                     cell.second->params[id_INIT_L20] = Property(LUT_D1, 4);
+                printf("L00 %04b\n",int_or_default(cell.second->params, id_INIT_L00, 0));
+                printf("L01 %04b\n",int_or_default(cell.second->params, id_INIT_L01, 0));
+                printf("L10 %04b\n",int_or_default(cell.second->params, id_INIT_L10, 0));
+                if (cell.second->getPort(id_D0_10)) {
+                    
+                }
             }
             cell.second->params[id_L2T4_UPPER] = Property((l.z == CPE_LT_U_Z) ? 1 : 0, 1);
         } else if (cell.second->type.in(id_CPE_LT_L)) {
diff --git a/himbaechel/uarch/gatemate/pack_cpe.cc b/himbaechel/uarch/gatemate/pack_cpe.cc
index dbc62492..de131a73 100644
--- a/himbaechel/uarch/gatemate/pack_cpe.cc
+++ b/himbaechel/uarch/gatemate/pack_cpe.cc
@@ -202,10 +202,10 @@ void GateMatePacker::pack_cpe()
         bool is_l2t5 = false;
         if (ci.type == id_CC_L2T5) {
             l2t5_list.push_back(&ci);
-            ci.renamePort(id_I0, id_IN1);
-            ci.renamePort(id_I1, id_IN2);
-            ci.renamePort(id_I2, id_IN3);
-            ci.renamePort(id_I3, id_IN4);
+            ci.renamePort(id_I0, id_D0_00);
+            ci.renamePort(id_I1, id_D1_00);
+            ci.renamePort(id_I2, id_D0_01);
+            ci.renamePort(id_I3, id_D1_01);
 
             ci.renamePort(id_O, id_OUT);
             rename_param(&ci, id_INIT_L02, id_INIT_L00, 4);
@@ -217,12 +217,12 @@ void GateMatePacker::pack_cpe()
             ci.type = id_CPE_L2T4;
             is_l2t5 = true;
         } else if (ci.type == id_CC_MX2) {
-            ci.renamePort(id_D1, id_IN1);
+            ci.renamePort(id_D1, id_D0_00);
             NetInfo *sel = ci.getPort(id_S0);
-            ci.renamePort(id_S0, id_IN2);
-            ci.addInput(id_IN3);
-            ci.connectPort(id_IN3, sel);
-            ci.renamePort(id_D0, id_IN4);
+            ci.renamePort(id_S0, id_D1_00);
+            ci.addInput(id_D0_01);
+            ci.connectPort(id_D0_01, sel);
+            ci.renamePort(id_D0, id_D1_01);
             ci.disconnectPort(id_D1);
             ci.params[id_INIT_L00] = Property(LUT_AND, 4);
             ci.params[id_INIT_L01] = Property(LUT_AND_INV_D0, 4);
@@ -230,18 +230,22 @@ void GateMatePacker::pack_cpe()
             ci.renamePort(id_Y, id_OUT);
             ci.type = id_CPE_L2T4;
         } else {
-            ci.renamePort(id_I0, id_IN1);
-            ci.renamePort(id_I1, id_IN2);
-            ci.renamePort(id_I2, id_IN3);
-            ci.renamePort(id_I3, id_IN4);
             ci.renamePort(id_O, id_OUT);
             if (ci.type.in(id_CC_LUT1, id_CC_LUT2)) {
+                ci.renamePort(id_I0, id_D0_10);
+                ci.renamePort(id_I1, id_D1_10);
                 uint8_t val = int_or_default(ci.params, id_INIT, 0);
                 if (ci.type == id_CC_LUT1)
                     val = val << 2 | val;
                 ci.params[id_INIT_L00] = Property(val, 4);
                 ci.unsetParam(id_INIT);
                 ci.params[id_INIT_L10] = Property(LUT_D0, 4);
+            } else {
+                ci.renamePort(id_I0, id_D0_00);
+                ci.renamePort(id_I1, id_D1_00);
+                ci.renamePort(id_I2, id_D0_01);
+                ci.renamePort(id_I3, id_D1_01);
+
             }
             ci.type = id_CPE_L2T4;
         }
@@ -297,8 +301,8 @@ void GateMatePacker::pack_cpe()
         upper->region = ci->region;
         upper->constr_abs_z = true;
         upper->constr_z = CPE_LT_U_Z;
-        ci->movePortTo(id_I4, upper, id_IN1);
-        upper->params[id_INIT_L00] = Property(LUT_D0, 4);
+        ci->movePortTo(id_I4, upper, id_D0_10);
+        //upper->params[id_INIT_L00] = Property(LUT_D0, 4);
         upper->params[id_INIT_L10] = Property(LUT_D0, 4);
         ci->constr_children.push_back(upper);
 
@@ -322,8 +326,8 @@ void GateMatePacker::pack_cpe()
         ci.cluster = ci.name;
         ci.renamePort(id_Y, id_OUT);
 
-        ci.renamePort(id_S0, id_IN2); // IN6
-        ci.renamePort(id_S1, id_IN4); // IN8
+        ci.renamePort(id_S0, id_D1_00); // IN6
+        ci.renamePort(id_S1, id_D1_01); // IN8
 
         uint8_t select = 0;
         uint8_t invert = 0;
@@ -355,10 +359,10 @@ void GateMatePacker::pack_cpe()
         upper->params[id_INIT_L10] = Property(select, 4); // Selection bits
         upper->params[id_C_FUNCTION] = Property(C_MX4, 3);
 
-        ci.movePortTo(id_D0, upper, id_IN1);
-        ci.movePortTo(id_D1, upper, id_IN2);
-        ci.movePortTo(id_D2, upper, id_IN3);
-        ci.movePortTo(id_D3, upper, id_IN4);
+        ci.movePortTo(id_D0, upper, id_M1);
+        ci.movePortTo(id_D1, upper, id_M2);
+        ci.movePortTo(id_D2, upper, id_M3);
+        ci.movePortTo(id_D3, upper, id_M4);
         ci.constr_children.push_back(upper);
 
         NetInfo *o = ci.getPort(id_OUT);
@@ -389,16 +393,15 @@ void GateMatePacker::pack_cpe()
         ci.renamePort(id_Q, id_DOUT);
         NetInfo *d_net = ci.getPort(id_D);
         if (d_net == net_PACKER_GND) {
-            lt->params[id_INIT_L00] = Property(LUT_ZERO, 4);
+            lt->params[id_INIT_L10] = Property(LUT_ZERO, 4);
             ci.disconnectPort(id_D);
         } else if (d_net == net_PACKER_VCC) {
-            lt->params[id_INIT_L00] = Property(LUT_ONE, 4);
+            lt->params[id_INIT_L10] = Property(LUT_ONE, 4);
             ci.disconnectPort(id_D);
         } else {
-            lt->params[id_INIT_L00] = Property(LUT_D0, 4);
+            lt->params[id_INIT_L10] = Property(LUT_D0, 4);
+            ci.movePortTo(id_D, lt, id_D0_00);
         }
-        lt->params[id_INIT_L10] = Property(LUT_D0, 4);
-        ci.movePortTo(id_D, lt, id_IN1);
         ci.type = (ci.type == id_CC_DLT) ? id_CPE_LATCH : id_CPE_FF;
         NetInfo *conn = ctx->createNet(ctx->idf("%s$di", ci.name.c_str(ctx)));
         lt->connectPort(id_OUT, conn);
@@ -804,16 +807,16 @@ std::pair<CellInfo *, CellInfo *> GateMatePacker::move_ram_o(CellInfo *cell, IdS
             ctx->bindBel(b, cpe_half, PlaceStrength::STRENGTH_FIXED);
         }
         if (net == net_PACKER_GND) {
-            cpe_half->params[id_INIT_L00] = Property(LUT_ZERO, 4);
+            cpe_half->params[id_INIT_L10] = Property(LUT_ZERO, 4);
             cell->disconnectPort(origPort);
         } else if (net == net_PACKER_VCC) {
-            cpe_half->params[id_INIT_L00] = Property(LUT_ONE, 4);
+            cpe_half->params[id_INIT_L10] = Property(LUT_ONE, 4);
             cell->disconnectPort(origPort);
         } else {
-            cpe_half->params[id_INIT_L00] = Property(LUT_D0, 4);
-            cell->movePortTo(origPort, cpe_half, id_IN1);
+            cpe_half->params[id_INIT_L10] = Property(LUT_D0, 4);
+            cell->movePortTo(origPort, cpe_half, id_D0_10);
         }
-        cpe_half->params[id_INIT_L10] = Property(LUT_D0, 4);
+        
 
         cpe_ramio->params[id_C_RAM_O] = Property(1, 1);
         NetInfo *ram_o = ctx->createNet(ctx->idf("%s$ram_o", cpe_half->name.c_str(ctx)));
@@ -867,16 +870,15 @@ std::pair<CellInfo *, CellInfo *> GateMatePacker::move_ram_io(CellInfo *cell, Id
 
     if (o_net) {
         if (o_net == net_PACKER_GND) {
-            cpe_half->params[id_INIT_L00] = Property(LUT_ZERO, 4);
+            cpe_half->params[id_INIT_L10] = Property(LUT_ZERO, 4);
             cell->disconnectPort(oPort);
         } else if (o_net == net_PACKER_VCC) {
-            cpe_half->params[id_INIT_L00] = Property(LUT_ONE, 4);
+            cpe_half->params[id_INIT_L10] = Property(LUT_ONE, 4);
             cell->disconnectPort(oPort);
         } else {
-            cpe_half->params[id_INIT_L00] = Property(LUT_D0, 4);
-            cell->movePortTo(oPort, cpe_half, id_IN1);
+            cpe_half->params[id_INIT_L10] = Property(LUT_D0, 4);
+            cell->movePortTo(oPort, cpe_half, id_D0_10);
         }
-        cpe_half->params[id_INIT_L10] = Property(LUT_D0, 4);
         cpe_ramio->params[id_C_RAM_O] = Property(1, 1);
 
         NetInfo *ram_o = ctx->createNet(ctx->idf("%s$ram_o", cpe_half->name.c_str(ctx)));