diff --git a/himbaechel/uarch/xilinx/xilinx.cc b/himbaechel/uarch/xilinx/xilinx.cc
index 1ebccb6a..ab3b5a2a 100644
--- a/himbaechel/uarch/xilinx/xilinx.cc
+++ b/himbaechel/uarch/xilinx/xilinx.cc
@@ -760,7 +760,9 @@ delay_t XilinxImpl::estimateDelay(WireId src, WireId dst) const
     }
 
     // TODO: improve sophistication here based on old nextpnr-xilinx code
-    return 800 + 50 * (std::abs(dy - sy) + std::abs(dx - sx));
+    int dist_x = std::abs(dx - sx), dist_y = std::abs(dy - sy);
+    return 500 + 12 * (2 * std::max(dist_y - 6, 0) + 4 * std::min(dist_y, 6)
+        + std::max(dist_x - 12, 0) + 2 * std::min(dist_x, 12));
 }
 
 delay_t XilinxImpl::predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel, IdString dst_pin) const
@@ -769,7 +771,7 @@ delay_t XilinxImpl::predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel,
     tile_xy(ctx->chip_info, src_bel.tile, sx, sy);
     tile_xy(ctx->chip_info, dst_bel.tile, dx, dy);
     // TODO: improve sophistication here based on old nextpnr-xilinx code
-    return 500 + 50 * (std::abs(dy - sy) + std::abs(dx - sx));
+    return 500 + 25 * (2 * std::abs(dy - sy) + std::abs(dx - sx));
 }
 
 BoundingBox XilinxImpl::getRouteBoundingBox(WireId src, WireId dst) const