From f177c39c0bdbfb92bae0c981369cb60511ca7435 Mon Sep 17 00:00:00 2001 From: gatecat Date: Wed, 4 Mar 2026 09:54:20 +0100 Subject: [PATCH] xilinx: Mark global buffers as such for HeAP/SA Signed-off-by: gatecat --- himbaechel/uarch/xilinx/gen/filters.py | 6 +++++- himbaechel/uarch/xilinx/gen/xilinx_gen.py | 4 ++++ 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/himbaechel/uarch/xilinx/gen/filters.py b/himbaechel/uarch/xilinx/gen/filters.py index 01fd91e4..3299a610 100644 --- a/himbaechel/uarch/xilinx/gen/filters.py +++ b/himbaechel/uarch/xilinx/gen/filters.py @@ -103,4 +103,8 @@ def include_pip(tile_type, p): return False if "MMCM_CLK_FREQ_BB" in p.dst_wire().name(): return False - return True \ No newline at end of file + return True + +def is_global_bel(bel): + bt = bel.bel_type() + return bt in ("BUFGCTRL_BUFGCTRL", "BUFG_BUFG") diff --git a/himbaechel/uarch/xilinx/gen/xilinx_gen.py b/himbaechel/uarch/xilinx/gen/xilinx_gen.py index a8a5b6d2..9ae8fa5b 100644 --- a/himbaechel/uarch/xilinx/gen/xilinx_gen.py +++ b/himbaechel/uarch/xilinx/gen/xilinx_gen.py @@ -125,11 +125,13 @@ def import_tiletype(ch: Chip, tile: xilinx_device.Tile): gnd = tt.create_bel(f"PSEUDO_GND", f"PSEUDO_GND", z=0) gnd.site = -1 gnd.extra_data = BelExtraData(name_in_site=ch.strs.id("PSEUDO_GND")) + gnd.flags |= BEL_FLAG_GLOBAL tt.add_bel_pin(gnd, "Y", "GND", PinType.OUTPUT) vcc = tt.create_bel(f"PSEUDO_VCC", f"PSEUDO_VCC", z=1) vcc.site = -1 vcc.extra_data = BelExtraData(name_in_site=ch.strs.id("PSEUDO_VCC")) + vcc.flags |= BEL_FLAG_GLOBAL tt.add_bel_pin(vcc, "Y", "VCC", PinType.OUTPUT) def add_pip(src_wire, dst_wire, pip_class=PipClass.TILE_ROUTING, timing="", site_key=-1, bel_name="", pip_config=0): @@ -205,6 +207,8 @@ def import_tiletype(ch: Chip, tile: xilinx_device.Tile): nb.site = variant_key nb.extra_data = BelExtraData(name_in_site=ch.strs.id(bel_name)) if bel.bel_class() == "RBEL": nb.flags |= 2 + if filters.is_global_bel(bel): + nb.flags |= BEL_FLAG_GLOBAL # TODO: extra data (site etc) for pin in bel.pins(): tt.add_bel_pin(nb, pin.name, lookup_site_wire(pin.site_wire()), lookup_port_type(pin.dir()))