From e9bac6961a14b75d49d78cc5ed6c3fa18047de47 Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Sat, 4 Oct 2025 23:03:33 +1000
Subject: [PATCH] Gowin. GW5A series BSRAM fix. (#1564)

In the new series of chips, the SemiDual Port primitive has one RESET
pin instead of two in previous versions - RESETA and RESETB.

Physically, the two pins are still there and both must be connected,
with RESETA being constant.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 himbaechel/uarch/gowin/gowin.h           | 1 +
 himbaechel/uarch/gowin/gowin_arch_gen.py | 3 +++
 himbaechel/uarch/gowin/gowin_utils.cc    | 6 ++++++
 himbaechel/uarch/gowin/gowin_utils.h     | 1 +
 himbaechel/uarch/gowin/pack.cc           | 7 +++++++
 5 files changed, 18 insertions(+)

diff --git a/himbaechel/uarch/gowin/gowin.h b/himbaechel/uarch/gowin/gowin.h
index 52094314..4a4390e7 100644
--- a/himbaechel/uarch/gowin/gowin.h
+++ b/himbaechel/uarch/gowin/gowin.h
@@ -203,6 +203,7 @@ NPNR_PACKED_STRUCT(struct Extra_chip_data_POD {
     static constexpr int32_t HAS_PINCFG = 128;
     static constexpr int32_t HAS_DFF67 = 256;
     static constexpr int32_t HAS_CIN_MUX = 512;
+    static constexpr int32_t NEED_BSRAM_RESET_FIX = 1024;
 });
 
 } // namespace
diff --git a/himbaechel/uarch/gowin/gowin_arch_gen.py b/himbaechel/uarch/gowin/gowin_arch_gen.py
index c27de274..f14a0c05 100644
--- a/himbaechel/uarch/gowin/gowin_arch_gen.py
+++ b/himbaechel/uarch/gowin/gowin_arch_gen.py
@@ -28,6 +28,7 @@ CHIP_HAS_CLKDIV_HCLK       = 0x40
 CHIP_HAS_PINCFG            = 0x80
 CHIP_HAS_DFF67             = 0x100
 CHIP_HAS_CIN_MUX           = 0x200
+CHIP_NEED_BSRAM_RESET_FIX  = 0x400
 
 # Tile flags
 TILE_I3C_CAPABLE_IO        = 0x1
@@ -1614,6 +1615,8 @@ def main():
             chip_flags |= CHIP_HAS_DFF67;
         if "HAS_CIN_MUX" in db.chip_flags:
             chip_flags |= CHIP_HAS_CIN_MUX;
+        if "NEED_BSRAM_RESET_FIX" in db.chip_flags:
+            chip_flags |= CHIP_NEED_BSRAM_RESET_FIX;
 
     X = db.cols;
     Y = db.rows;
diff --git a/himbaechel/uarch/gowin/gowin_utils.cc b/himbaechel/uarch/gowin/gowin_utils.cc
index 9bf06c6b..c81f3939 100644
--- a/himbaechel/uarch/gowin/gowin_utils.cc
+++ b/himbaechel/uarch/gowin/gowin_utils.cc
@@ -386,6 +386,12 @@ bool GowinUtils::need_BSRAM_OUTREG_fix(void)
     return extra->chip_flags & Extra_chip_data_POD::NEED_BSRAM_OUTREG_FIX;
 }
 
+bool GowinUtils::need_BSRAM_RESET_fix(void)
+{
+    const Extra_chip_data_POD *extra = reinterpret_cast<const Extra_chip_data_POD *>(ctx->chip_info->extra_data.get());
+    return extra->chip_flags & Extra_chip_data_POD::NEED_BSRAM_RESET_FIX;
+}
+
 bool GowinUtils::need_BLKSEL_fix(void)
 {
     const Extra_chip_data_POD *extra = reinterpret_cast<const Extra_chip_data_POD *>(ctx->chip_info->extra_data.get());
diff --git a/himbaechel/uarch/gowin/gowin_utils.h b/himbaechel/uarch/gowin/gowin_utils.h
index 425162d4..be40e62a 100644
--- a/himbaechel/uarch/gowin/gowin_utils.h
+++ b/himbaechel/uarch/gowin/gowin_utils.h
@@ -100,6 +100,7 @@ struct GowinUtils
     bool has_SP32(void);
     bool need_SP_fix(void);
     bool need_BSRAM_OUTREG_fix(void);
+    bool need_BSRAM_RESET_fix(void);
     bool need_BLKSEL_fix(void);
     bool has_PLL_HCLK(void);
     bool has_CLKDIV_HCLK(void);
diff --git a/himbaechel/uarch/gowin/pack.cc b/himbaechel/uarch/gowin/pack.cc
index 6530615d..9698c551 100644
--- a/himbaechel/uarch/gowin/pack.cc
+++ b/himbaechel/uarch/gowin/pack.cc
@@ -2632,6 +2632,13 @@ struct GowinPacker
             ci->connectPort(id_WREB, vss_net);
             bsram_rename_ports(ci, bit_width, "DO[%d]", "DO%d", 18);
         }
+
+        // If misconnected RESET
+        if (gwu.need_BSRAM_RESET_fix()) {
+            ci->renamePort(id_RESET, id_RESETB);
+            ci->addInput(id_RESET);
+            ci->connectPort(id_RESET, vcc_net);
+        }
     }
 
     void pack_DPB(CellInfo *ci)