From e73506104bdc34711c549dfc89b816fb5aeeb6ab Mon Sep 17 00:00:00 2001
From: Josef Gajdusek <atx@atx.name>
Date: Sat, 25 Apr 2026 00:09:17 +0200
Subject: [PATCH] generic: Improve the example for K != 4

Configuring K < 4 used to result in "dangling" inputs to the cells being
generated (those are just not driven by anything in the resulting Verilog/JSON).

Configuring K > 4 used to result in an assertion crash in cells.cc.

The ctx.setLutK call fixes both cases.
---
 generic/examples/simple.py  | 2 ++
 generic/examples/simple.sh  | 3 ++-
 generic/examples/simtest.sh | 3 ++-
 3 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/generic/examples/simple.py b/generic/examples/simple.py
index 4b7f4025..654d395d 100644
--- a/generic/examples/simple.py
+++ b/generic/examples/simple.py
@@ -3,6 +3,8 @@ from simple_config import *
 def is_io(x, y):
 	return x == 0 or x == X-1 or y == 0 or y == Y-1
 
+ctx.setLutK(K)
+
 for x in range(X):
 	for y in range(Y):
 		# Bel port wires
diff --git a/generic/examples/simple.sh b/generic/examples/simple.sh
index f23dd02a..c9e38c1a 100755
--- a/generic/examples/simple.sh
+++ b/generic/examples/simple.sh
@@ -1,6 +1,7 @@
 #!/usr/bin/env bash
 set -ex
 export PYTHONPATH=$(dirname $0)
-yosys -p "tcl ../synth/synth_generic.tcl 4 blinky.json" blinky.v
+K=$(python3 -c "import simple_config; print(simple_config.K)")
+yosys -p "tcl ../synth/synth_generic.tcl $K blinky.json" blinky.v
 ${NEXTPNR:-../../nextpnr-generic} --pre-pack simple.py --pre-place simple_timing.py --json blinky.json --post-route bitstream.py --write pnrblinky.json
 yosys -p "read_verilog -lib ../synth/prims.v; read_json pnrblinky.json; dump -o blinky.il; show -format png -prefix blinky"
diff --git a/generic/examples/simtest.sh b/generic/examples/simtest.sh
index be271902..e66fd2fb 100755
--- a/generic/examples/simtest.sh
+++ b/generic/examples/simtest.sh
@@ -1,7 +1,8 @@
 #!/usr/bin/env bash
 set -ex
 export PYTHONPATH=$(dirname $0)
-yosys -p "tcl ../synth/synth_generic.tcl 4 blinky.json" blinky.v
+K=$(python3 -c "import simple_config; print(simple_config.K)")
+yosys -p "tcl ../synth/synth_generic.tcl $K blinky.json" blinky.v
 ${NEXTPNR:-../../nextpnr-generic} --no-iobs --pre-pack simple.py --pre-place simple_timing.py --json blinky.json --post-route bitstream.py --write pnrblinky.json
 yosys -p "read_json pnrblinky.json; write_verilog -noattr -norename pnrblinky.v"
 iverilog -o blinky_simtest ../synth/prims.v blinky_tb.v pnrblinky.v