diff --git a/xc7/attosoc.pcf b/xc7/attosoc.pcf
index 3ef75a17..fd14331c 100644
--- a/xc7/attosoc.pcf
+++ b/xc7/attosoc.pcf
@@ -2,8 +2,7 @@ COMP "led[0]" LOCATE = SITE "M14" LEVEL 1;
 COMP "led[1]" LOCATE = SITE "M15" LEVEL 1;
 COMP "led[2]" LOCATE = SITE "G14" LEVEL 1;
 COMP "led[3]" LOCATE = SITE "D18" LEVEL 1;
-COMP "clk" LOCATE = SITE "K17" LEVEL 1;
-COMP "pll.mmcm_adv_inst" LOCATE = SITE "MMCME2_ADV_X1Y2" LEVEL 1;
+COMP "clki" LOCATE = SITE "K17" LEVEL 1;
 NET "pll.clkin1" PERIOD = 8 nS ;
-#PIN "clk_pin" = BEL "clk.PAD" PINNAME PAD;
-#PIN "clk_pin" CLOCK_DEDICATED_ROUTE = FALSE;
+PIN "clki_pin" = BEL "clki.PAD" PINNAME PAD;
+PIN "clki_pin" CLOCK_DEDICATED_ROUTE = FALSE;
diff --git a/xc7/attosoc.sh b/xc7/attosoc.sh
index e7f1c95a..119ed6b9 100755
--- a/xc7/attosoc.sh
+++ b/xc7/attosoc.sh
@@ -1,11 +1,14 @@
 #!/bin/bash
-#set -ex
-#rm -f picorv32.v
-#wget https://raw.githubusercontent.com/cliffordwolf/picorv32/master/picorv32.v
+set -ex
+rm -f picorv32.v attosoc.v
+wget https://raw.githubusercontent.com/cliffordwolf/picorv32/master/picorv32.v
+wget https://raw.githubusercontent.com/SymbiFlow/prjtrellis/master/examples/picorv32_versa5g/attosoc.v
 yosys attosoc.ys
-../nextpnr-xc7 --json attosoc.json --xdl attosoc.xdl --pcf attosoc.pcf --freq 150 |& tee attosoc.log
+set +e
+../nextpnr-xc7 --json attosoc.json --xdl attosoc.xdl --pcf attosoc.pcf --freq 125
+set -e
 xdl -xdl2ncd attosoc.xdl
-bitgen -w attosoc.ncd -g UnconstrainedPins:Allow
+#bitgen -w attosoc.ncd -g UnconstrainedPins:Allow
 trce attosoc.ncd -v 10
 
 netgen -sim -ofmt vhdl attosoc.ncd -w attosoc_pnr.vhd
diff --git a/xc7/attosoc.ys b/xc7/attosoc.ys
index 105728c9..7ec25173 100644
--- a/xc7/attosoc.ys
+++ b/xc7/attosoc.ys
@@ -1,7 +1,6 @@
 read_verilog attosoc_top.v
 read_verilog attosoc.v
 read_verilog picorv32.v
-read_verilog 125MHz_to_60MHz.v
 
 #synth_xilinx -top picorv32
 
diff --git a/xc7/attosoc_tb.vhd b/xc7/attosoc_tb.vhd
index fe697c3f..68996189 100644
--- a/xc7/attosoc_tb.vhd
+++ b/xc7/attosoc_tb.vhd
@@ -14,7 +14,7 @@ begin
         wait for 4 ns;
     end process;
 
-    uut: entity work.name port map(clk_PAD_PAD => clk, led_0_OUTBUF_OUT => led(0), led_1_OUTBUF_OUT => led(1), led_2_OUTBUF_OUT => led(2), led_3_OUTBUF_OUT => led(3));
+    uut: entity work.name port map(clki_PAD_PAD => clk, led_0_OUTBUF_OUT => led(0), led_1_OUTBUF_OUT => led(1), led_2_OUTBUF_OUT => led(2), led_3_OUTBUF_OUT => led(3));
 
 process
 begin
diff --git a/xc7/attosoc_top.v b/xc7/attosoc_top.v
index b794abda..bbf75a05 100644
--- a/xc7/attosoc_top.v
+++ b/xc7/attosoc_top.v
@@ -1,15 +1,24 @@
 module top (
-	input clk,
+	input clki,
 	output [3:0] led
 );
 
     (* keep *)
     wire led_unused;
 
-    wire gclk;
-    clk_wiz_v3_6 pll(.CLK_IN1(clk), .CLK_OUT1(gclk));
-    //assign gclk = clk;
-    attosoc soc(.clk(gclk), .led({led_unused, led}));
+    wire clk;
+    BUFGCTRL clk_gb (
+        .I0(clki),
+        .CE0(1'b1),
+        .CE1(1'b0),
+        .S0(1'b1),
+        .S1(1'b0),
+        .IGNORE0(1'b0),
+        .IGNORE1(1'b0),
+        .O(clk)
+    );
+
+    attosoc soc(.clk(clk), .led({led_unused, led}));
 
 endmodule