From c2e8bc89c0ed7fe273f7180d3001dd61f34204dd Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Mon, 23 Jun 2025 08:59:45 +0200 Subject: [PATCH] Cleanups --- himbaechel/uarch/gatemate/bitstream.cc | 11 +++++++-- himbaechel/uarch/gatemate/cells.cc | 4 +-- himbaechel/uarch/gatemate/constids.inc | 19 +++++++++++--- himbaechel/uarch/gatemate/gatemate.cc | 34 +++++++++++++++++++++----- himbaechel/uarch/gatemate/pack_cpe.cc | 6 ++--- 5 files changed, 58 insertions(+), 16 deletions(-) diff --git a/himbaechel/uarch/gatemate/bitstream.cc b/himbaechel/uarch/gatemate/bitstream.cc index 4e8a6858..ae62578e 100644 --- a/himbaechel/uarch/gatemate/bitstream.cc +++ b/himbaechel/uarch/gatemate/bitstream.cc @@ -243,12 +243,19 @@ struct BitstreamBackend break; case id_CPE_L2T4.index: case id_CPE_L2T5.index: + case id_CPE_ADDF.index: + case id_CPE_ADDF2.index: + case id_CPE_MULT.index: + case id_CPE_MX4.index: + case id_CPE_EN_CIN.index: + case id_CPE_CONCAT.index: + case id_CPE_ADDCIN.index: + case id_CPE_CI.index: case id_CPE_FF.index: case id_CPE_RAMI.index: case id_CPE_RAMO.index: case id_CPE_RAMIO.index: - case id_CPE_LT_U.index: - case id_CPE_LT_L.index: { + { // Update configuration bits based on signal inversion dict params = cell.second->params; uint8_t func = int_or_default(cell.second->params, id_C_FUNCTION, 0); diff --git a/himbaechel/uarch/gatemate/cells.cc b/himbaechel/uarch/gatemate/cells.cc index f87ada5d..c8417fea 100644 --- a/himbaechel/uarch/gatemate/cells.cc +++ b/himbaechel/uarch/gatemate/cells.cc @@ -33,7 +33,7 @@ CellInfo *GateMatePacker::create_cell_ptr(IdString type, IdString name) cell->ports[id].name = id; cell->ports[id].type = dir; }; - if (type.in(id_CPE_LT, id_CPE_LT_U, id_CPE_LT_L, id_CPE_L2T4, id_CPE_L2T5_U, id_CPE_L2T5_L)) { + if (type.in(id_CPE_LT, id_CPE_LT_U, id_CPE_LT_L, id_CPE_L2T4, id_CPE_L2T5_U, id_CPE_L2T5_L, id_CPE_CI)) { add_port(id_I1, PORT_IN); add_port(id_I2, PORT_IN); add_port(id_I3, PORT_IN); @@ -44,7 +44,7 @@ CellInfo *GateMatePacker::create_cell_ptr(IdString type, IdString name) add_port(id_EN, PORT_IN); add_port(id_CLK, PORT_IN); add_port(id_SR, PORT_IN); - if (type == id_CPE_LT_L) { + if (type.in(id_CPE_LT_L, id_CPE_CI)) { add_port(id_COUTY1, PORT_OUT); } } else if (type.in(id_CLKIN)) { diff --git a/himbaechel/uarch/gatemate/constids.inc b/himbaechel/uarch/gatemate/constids.inc index 3e0cd9e8..c047c216 100644 --- a/himbaechel/uarch/gatemate/constids.inc +++ b/himbaechel/uarch/gatemate/constids.inc @@ -911,7 +911,7 @@ X(IN2) X(IN3) X(IN4) X(OUT) -X(CP_OUT) +X(CPOUT) // hardware primitive CPE_FF_U X(CPE_FF_U) @@ -938,8 +938,8 @@ X(CPE_LT_L) //X(IN3) //X(IN4) //X(OUT) -//X(CP_OUT) -X(MUX_OUT) +//X(CPOUT) +X(MUXOUT) X(CINY1) X(COUTY1) @@ -973,6 +973,11 @@ X(IN7) X(IN8) X(OUT1) X(OUT2) +X(CPOUT1) +X(CPOUT2) +//X(MUXOUT) +//X(CINY1) +//X(COUTY1) // hardware primitive CPE_LINES X(CPE_LINES) @@ -2223,3 +2228,11 @@ X(CPE_L2T4) X(CPE_L2T5) X(CPE_L2T5_U) X(CPE_L2T5_L) +X(CPE_ADDF) +X(CPE_ADDF2) +X(CPE_MULT) +X(CPE_MX4) +X(CPE_EN_CIN) +X(CPE_CONCAT) +X(CPE_ADDCIN) +X(CPE_CI) \ No newline at end of file diff --git a/himbaechel/uarch/gatemate/gatemate.cc b/himbaechel/uarch/gatemate/gatemate.cc index 4520caa0..680fc572 100644 --- a/himbaechel/uarch/gatemate/gatemate.cc +++ b/himbaechel/uarch/gatemate/gatemate.cc @@ -223,28 +223,50 @@ void GateMateImpl::postPlace() } std::vector delete_cells; for (auto &cell : ctx->cells) { - if (cell.second->type == id_CPE_L2T5_L) { + if (cell.second->type.in(id_CPE_L2T5_L,id_CPE_LT_L)) { BelId bel = cell.second->bel; PlaceStrength strength = cell.second->belStrength; + uint8_t func = int_or_default(cell.second->params, id_C_FUNCTION, 0); + bool is_l2t5 = cell.second->type == id_CPE_L2T5_L; Loc loc = ctx->getBelLocation(bel); loc.z = 7; // CPE_LT_FULL ctx->unbindBel(bel); - cell.second->type = id_CPE_L2T5; ctx->bindBel(ctx->getBelByLocation(loc), cell.second.get(), strength); cell.second->renamePort(id_IN1, id_IN5); cell.second->renamePort(id_IN2, id_IN6); cell.second->renamePort(id_IN3, id_IN7); cell.second->renamePort(id_IN4, id_IN8); cell.second->renamePort(id_OUT, id_OUT1); + if (is_l2t5) { + cell.second->type = id_CPE_L2T5; + } else { + switch(func) { + case C_ADDF : cell.second->type = id_CPE_ADDF; break; + case C_ADDF2 : cell.second->type = id_CPE_ADDF2; break; + case C_MULT : cell.second->type = id_CPE_MULT; break; + case C_MX4 : cell.second->type = id_CPE_MX4; break; + case C_EN_CIN : cell.second->type = id_CPE_EN_CIN; break; + case C_CONCAT : cell.second->type = id_CPE_CONCAT; break; + case C_ADDCIN : cell.second->type = id_CPE_ADDCIN; break; + default: + break; + } + } loc.z = 0; CellInfo *upper = ctx->getBoundBelCell(ctx->getBelByLocation(loc)); cell.second->params[id_INIT_L00] = Property(int_or_default(upper->params, id_INIT_L00, 0), 4); + cell.second->params[id_INIT_L01] = Property(int_or_default(upper->params, id_INIT_L01, 0), 4); cell.second->params[id_INIT_L10] = Property(int_or_default(upper->params, id_INIT_L10, 0), 4); upper->movePortTo(id_IN1, cell.second.get(), id_IN1); + upper->movePortTo(id_IN2, cell.second.get(), id_IN2); + upper->movePortTo(id_IN3, cell.second.get(), id_IN3); + upper->movePortTo(id_IN4, cell.second.get(), id_IN4); + upper->movePortTo(id_OUT, cell.second.get(), id_OUT2); + } // Mark for deletion - if (cell.second->type == id_CPE_L2T5_U) { + if (cell.second->type.in(id_CPE_L2T5_U,id_CPE_LT_U)) { delete_cells.push_back(cell.second->name); } } @@ -313,7 +335,7 @@ IdString GateMateImpl::getBelBucketForCellType(IdString cell_type) const if (cell_type.in(id_CPE_IBUF, id_CPE_OBUF, id_CPE_TOBUF, id_CPE_IOBUF, id_CPE_LVDS_IBUF, id_CPE_LVDS_TOBUF, id_CPE_LVDS_OBUF, id_CPE_LVDS_IOBUF)) return id_GPIO; - else if (cell_type.in(id_CPE_LT_U, id_CPE_LT_L, id_CPE_LT, id_CPE_L2T4, id_CPE_L2T5_L, id_CPE_L2T5_U)) + else if (cell_type.in(id_CPE_LT_U, id_CPE_LT_L, id_CPE_LT, id_CPE_L2T4, id_CPE_L2T5_L, id_CPE_L2T5_U, id_CPE_CI)) return id_CPE_LT; else if (cell_type.in(id_CPE_FF_U, id_CPE_FF_L, id_CPE_FF)) return id_CPE_FF; @@ -326,7 +348,7 @@ IdString GateMateImpl::getBelBucketForCellType(IdString cell_type) const BelBucketId GateMateImpl::getBelBucketForBel(BelId bel) const { IdString bel_type = ctx->getBelType(bel); - if (bel_type.in(id_CPE_LT_U, id_CPE_LT_L, id_CPE_L2T4, id_CPE_L2T5_U, id_CPE_L2T5_L)) + if (bel_type.in(id_CPE_LT_U, id_CPE_LT_L)) return id_CPE_LT; else if (bel_type.in(id_CPE_FF_U, id_CPE_FF_L)) return id_CPE_FF; @@ -344,7 +366,7 @@ bool GateMateImpl::isValidBelForCellType(IdString cell_type, BelId bel) const else if (bel_type == id_CPE_LT_U) return cell_type.in(id_CPE_LT_U, id_CPE_LT, id_CPE_L2T4, id_CPE_L2T5_U); else if (bel_type == id_CPE_LT_L) - return cell_type.in(id_CPE_LT_L, id_CPE_LT, id_CPE_L2T4, id_CPE_L2T5_L); + return cell_type.in(id_CPE_LT_L, id_CPE_LT, id_CPE_L2T4, id_CPE_L2T5_L, id_CPE_CI); else if (bel_type == id_CPE_FF_U) return cell_type.in(id_CPE_FF_U, id_CPE_FF); else if (bel_type == id_CPE_FF_L) diff --git a/himbaechel/uarch/gatemate/pack_cpe.cc b/himbaechel/uarch/gatemate/pack_cpe.cc index 7fec79f0..75823c5c 100644 --- a/himbaechel/uarch/gatemate/pack_cpe.cc +++ b/himbaechel/uarch/gatemate/pack_cpe.cc @@ -399,12 +399,12 @@ void GateMatePacker::pack_addf() ci_upper->constr_z = -1; ci_upper->constr_y = -1; - CellInfo *ci_lower = create_cell_ptr(id_CPE_LT_L, ctx->idf("%s$ci_lower", root->name.c_str(ctx))); + CellInfo *ci_lower = create_cell_ptr(id_CPE_CI, ctx->idf("%s$ci_lower", root->name.c_str(ctx))); root->constr_children.push_back(ci_lower); ci_lower->cluster = root->name; ci_lower->constr_abs_z = false; ci_lower->constr_y = -1; - // TODO: Need to check C_O1 handling in this case + // TODO: Maybe move this to bitstream gen ci_lower->params[id_C_O1] = Property(0b11, 2); ci_lower->params[id_C_SELY1] = Property(1, 1); ci_lower->params[id_C_CY1_I] = Property(1, 1); @@ -556,7 +556,7 @@ void GateMatePacker::pack_addf() break; } } - cy->movePortTo(id_CO, upper, id_CP_OUT); + cy->movePortTo(id_CO, upper, id_CPOUT); } } }