From a3bccdd33df93b9173362831d5483291f7b1107c Mon Sep 17 00:00:00 2001 From: gatecat Date: Thu, 9 Apr 2026 14:22:06 +0200 Subject: [PATCH] xilinx: Use clock router for MMCMs too Signed-off-by: gatecat --- himbaechel/uarch/xilinx/pack_clocking.cc | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/himbaechel/uarch/xilinx/pack_clocking.cc b/himbaechel/uarch/xilinx/pack_clocking.cc index 1b3e7003..9a82ff67 100644 --- a/himbaechel/uarch/xilinx/pack_clocking.cc +++ b/himbaechel/uarch/xilinx/pack_clocking.cc @@ -231,10 +231,12 @@ void XilinxImpl::route_clocks() if ((clk_net->driver.cell->type.in(id_BUFGCTRL, id_BUFCE_BUFG_PS, id_BUFCE_BUFCE, id_BUFGCE_DIV_BUFGCE_DIV)) && clk_net->driver.port == id_O) is_global = true; - else if (clk_net->driver.cell->type == id_PLLE2_ADV_PLLE2_ADV && clk_net->users.entries() == 1 && + else if (clk_net->driver.cell->type.in(id_PLLE2_ADV_PLLE2_ADV, id_MMCME2_ADV_MMCME2_ADV) && + clk_net->users.entries() == 1 && ((*clk_net->users.begin()).cell->type.in(id_BUFGCTRL, id_BUFCE_BUFCE, id_BUFGCE_DIV_BUFGCE_DIV))) is_global = true; - else if (clk_net->users.entries() == 1 && (*clk_net->users.begin()).cell->type == id_PLLE2_ADV_PLLE2_ADV && + else if (clk_net->users.entries() == 1 && + (*clk_net->users.begin()).cell->type.in(id_PLLE2_ADV_PLLE2_ADV, id_MMCME2_ADV_MMCME2_ADV) && (*clk_net->users.begin()).port == id_CLKIN1) is_global = true; if (!is_global)