diff --git a/himbaechel/uarch/gatemate/gatemate.cc b/himbaechel/uarch/gatemate/gatemate.cc
index 5c97a66c..712e9817 100644
--- a/himbaechel/uarch/gatemate/gatemate.cc
+++ b/himbaechel/uarch/gatemate/gatemate.cc
@@ -56,18 +56,18 @@ void GateMateImpl::init_database(Arch *arch)
     fpga_mode = 3;
     timing_mode = 3;
 
-    static const std::map<std::string, int> fpga_map = {{"best", 1}, {"typical", 2}, {"worst", 3}};
-    static const std::map<std::string, int> timing_map = {{"lowpower", 1}, {"economy", 2}, {"speed", 3}};
+    static const std::map<std::string, int> fpga_map = {{"lowpower", 1}, {"economy", 2}, {"speed", 3}};
+    static const std::map<std::string, int> timing_map = {{"best", 1}, {"typical", 2}, {"worst", 3}};
 
     if (args.options.count("fpga_mode"))
         fpga_mode = parse_mode(args.options.at("fpga_mode"), fpga_map,
-                               "timing mode valid values are {1:best, 2:typical, 3:worst}");
+                               "operation mode valid values are {1:lowpower, 2:economy, 3:speed}");
     if (args.options.count("time_mode"))
         timing_mode = parse_mode(args.options.at("time_mode"), timing_map,
-                                 "operation mode valid values are {1:lowpower, 2:economy, 3:speed}");
+                                 "timing mode valid values are {1:best, 2:typical, 3:worst}");
 
     std::string speed_grade = "";
-    switch (fpga_mode) {
+    switch (timing_mode) {
     case 1:
         speed_grade = "best_";
         break;
@@ -78,12 +78,12 @@ void GateMateImpl::init_database(Arch *arch)
         speed_grade = "worst_";
         break;
     }
-    log_info("Using timing mode '%s'\n", fpga_mode == 1   ? "BEST"
-                                         : fpga_mode == 2 ? "TYPICAL"
-                                         : fpga_mode == 3 ? "WORST"
-                                                          : "");
+    log_info("Using timing mode '%s'\n", timing_mode == 1   ? "BEST"
+                                         : timing_mode == 2 ? "TYPICAL"
+                                         : timing_mode == 3 ? "WORST"
+                                                            : "");
 
-    switch (timing_mode) {
+    switch (fpga_mode) {
     case 1:
         speed_grade += "lpr";
         break;
@@ -93,10 +93,10 @@ void GateMateImpl::init_database(Arch *arch)
     default:
         speed_grade += "spd";
     }
-    log_info("Using operation mode '%s'\n", timing_mode == 1   ? "LOWPOWER"
-                                            : timing_mode == 2 ? "ECONOMY"
-                                            : timing_mode == 3 ? "SPEED"
-                                                               : "");
+    log_info("Using operation mode '%s'\n", fpga_mode == 1   ? "LOWPOWER"
+                                            : fpga_mode == 2 ? "ECONOMY"
+                                            : fpga_mode == 3 ? "SPEED"
+                                                             : "");
     arch->set_speed_grade(speed_grade);
 }
 
diff --git a/himbaechel/uarch/gatemate/pack_clocking.cc b/himbaechel/uarch/gatemate/pack_clocking.cc
index 117197d1..2b0a301f 100644
--- a/himbaechel/uarch/gatemate/pack_clocking.cc
+++ b/himbaechel/uarch/gatemate/pack_clocking.cc
@@ -364,7 +364,7 @@ void GateMatePacker::remove_clocking()
     flush_cells();
 }
 
-static const char *timing_mode_to_str(int mode)
+static const char *fpga_mode_to_str(int mode)
 {
     switch (mode) {
     case 1:
@@ -474,9 +474,9 @@ void GateMatePacker::pack_pll()
                 log_error("Unknown PERF_MD parameter value '%s' for cell %s.\n", mode.c_str(), ci.name.c_str(ctx));
             }
 
-            if (perf_md != uarch->timing_mode)
-                log_warning("PLL '%s' timing mode is '%s' but FPGA timing mode is '%s'.\n", ci.name.c_str(ctx),
-                            timing_mode_to_str(perf_md), timing_mode_to_str(uarch->timing_mode));
+            if (perf_md != uarch->fpga_mode)
+                log_warning("PLL '%s' operational mode is '%s' but FPGA operational mode is '%s'.\n",
+                            ci.name.c_str(ctx), fpga_mode_to_str(perf_md), fpga_mode_to_str(uarch->fpga_mode));
 
             double ref_clk = double_or_default(ci.params, id_REF_CLK, 0.0);
             if (ref_clk <= 0 || ref_clk > 125)