From 8ac7ed161a58dba197805ff79c0bb596e4cf18e8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Miodrag=20Milanovi=C4=87?= Date: Wed, 10 Sep 2025 14:04:42 +0200 Subject: [PATCH] gatemate: code cleanup and netlist fix (#1554) --- common/place/placer_heap.cc | 4 +++- himbaechel/uarch/gatemate/gatemate.cc | 14 +++++------ himbaechel/uarch/gatemate/gatemate.h | 4 +--- himbaechel/uarch/gatemate/pack_clocking.cc | 27 +++++++++++----------- 4 files changed, 24 insertions(+), 25 deletions(-) diff --git a/common/place/placer_heap.cc b/common/place/placer_heap.cc index a6e70c8f..f92f270f 100644 --- a/common/place/placer_heap.cc +++ b/common/place/placer_heap.cc @@ -1116,7 +1116,9 @@ class HeAPPlacer } for (auto &move : moves_made) { // Where we have ripped up cells; add them to the queue - if (move.second != nullptr && (move.second->cluster == ClusterId() || ctx->getClusterRootCell(move.second->cluster) == move.second)) + if (move.second != nullptr && + (move.second->cluster == ClusterId() || + ctx->getClusterRootCell(move.second->cluster) == move.second)) remaining.emplace(chain_size[move.second->name] * cfg.get_cell_legalisation_weight(ctx, move.second), move.second->name); diff --git a/himbaechel/uarch/gatemate/gatemate.cc b/himbaechel/uarch/gatemate/gatemate.cc index e724886b..490c4fd9 100644 --- a/himbaechel/uarch/gatemate/gatemate.cc +++ b/himbaechel/uarch/gatemate/gatemate.cc @@ -100,11 +100,6 @@ void GateMateImpl::init_database(Arch *arch) arch->set_speed_grade(speed_grade); } -const GateMateTileExtraDataPOD *GateMateImpl::tile_extra_data(int tile) const -{ - return reinterpret_cast(ctx->chip_info->tile_insts[tile].extra_data.get()); -} - void GateMateImpl::init(Context *ctx) { HimbaechelAPI::init(ctx); @@ -373,7 +368,6 @@ void GateMateImpl::postRoute() if (w.second.pip != PipId()) { const auto &extra_data = *pip_extra_data(w.second.pip); if (extra_data.type == PipExtra::PIP_EXTRA_MUX && (extra_data.flags & MUX_ROUTING)) { - this->cpe_bridges.insert({w.second.pip, ni->name}); nets_with_bridges.insert(ni->name); } } @@ -456,7 +450,8 @@ void GateMateImpl::expandBoundingBox(BoundingBox &bb) const bb.y1 = std::min((bb.y1 & 0xfffe) + 5, ctx->getGridDimY()); } -void GateMateImpl::configurePlacerHeap(PlacerHeapCfg &cfg) { +void GateMateImpl::configurePlacerHeap(PlacerHeapCfg &cfg) +{ cfg.chainRipup = true; cfg.placeAllAtOnce = true; } @@ -571,6 +566,11 @@ bool GateMateImpl::isPipInverting(PipId pip) const return extra_data.type == PipExtra::PIP_EXTRA_MUX && (extra_data.flags & MUX_INVERT); } +const GateMateTileExtraDataPOD *GateMateImpl::tile_extra_data(int tile) const +{ + return reinterpret_cast(ctx->chip_info->tile_insts[tile].extra_data.get()); +} + const GateMateBelExtraDataPOD *GateMateImpl::bel_extra_data(BelId bel) const { return reinterpret_cast(chip_bel_info(ctx->chip_info, bel).extra_data.get()); diff --git a/himbaechel/uarch/gatemate/gatemate.h b/himbaechel/uarch/gatemate/gatemate.h index 371cd1f9..acbaf06c 100644 --- a/himbaechel/uarch/gatemate/gatemate.h +++ b/himbaechel/uarch/gatemate/gatemate.h @@ -71,6 +71,7 @@ struct GateMateImpl : HimbaechelAPI bool isPipInverting(PipId pip) const override; const GateMateTileExtraDataPOD *tile_extra_data(int tile) const; + const GateMateBelExtraDataPOD *bel_extra_data(BelId bel) const; const GateMatePipExtraDataPOD *pip_extra_data(PipId pip) const; int get_dff_config(CellInfo *dff) const; @@ -87,7 +88,6 @@ struct GateMateImpl : HimbaechelAPI pool multiplier_zero_drivers; std::vector multipliers; std::vector used_cpes; - dict cpe_bridges; int fpga_mode; int timing_mode; @@ -106,8 +106,6 @@ struct GateMateImpl : HimbaechelAPI dict &wire_to_net, int &num); void repack(); - const GateMateBelExtraDataPOD *bel_extra_data(BelId bel) const; - bool get_delay_from_tmg_db(IdString id, DelayQuad &delay) const; void get_setuphold_from_tmg_db(IdString id_setup, IdString id_hold, DelayPair &setup, DelayPair &hold) const; void get_setuphold_from_tmg_db(IdString id_setuphold, DelayPair &setup, DelayPair &hold) const; diff --git a/himbaechel/uarch/gatemate/pack_clocking.cc b/himbaechel/uarch/gatemate/pack_clocking.cc index d0e09f7a..0fb285dc 100644 --- a/himbaechel/uarch/gatemate/pack_clocking.cc +++ b/himbaechel/uarch/gatemate/pack_clocking.cc @@ -136,8 +136,7 @@ void GateMatePacker::pack_bufg() int index = pad_info->flags - 1; die = uarch->tile_extra_data(in_net->driver.cell->bel.tile)->die; if (!clkin[die]->getPort(ctx->idf("CLK%d", index))) { - CellInfo *gpio = in_net->driver.cell->getPort(id_GPIO_IN)->driver.cell; - clkin[die]->connectPort(ctx->idf("CLK%d", index), gpio->getPort(id_I)); + clkin[die]->connectPort(ctx->idf("CLK%d", index), in_net->driver.cell->getPort(id_Y)); } } } @@ -313,7 +312,7 @@ void GateMatePacker::insert_pll_bufg() void GateMatePacker::remove_clocking() { log_info("Remove unused clocking cells..\n"); - auto remove_unused_cells = [&](std::vector &cells, const char *type) { + auto remove_unused_cells = [&](std::vector &cells) { for (auto cell : cells) { bool used = false; for (auto port : cell->ports) { @@ -330,8 +329,8 @@ void GateMatePacker::remove_clocking() } } }; - remove_unused_cells(clkin, "CLKIN"); - remove_unused_cells(glbout, "GLBOUT"); + remove_unused_cells(clkin); + remove_unused_cells(glbout); flush_cells(); } @@ -376,15 +375,7 @@ void GateMatePacker::pack_pll() } } - ci.cluster = ci.name; - ci.constr_abs_z = true; - ci.constr_z = 2 + pll_index[die]; // Position to a proper Z location - - Loc fixed_loc = uarch->locations[std::make_pair(ctx->idf("PLL%d", pll_index[die]), die)]; - BelId pll_bel = ctx->getBelByLocation(fixed_loc); - ctx->bindBel(pll_bel, &ci, PlaceStrength::STRENGTH_FIXED); - - if (pll_index[die] > 4) + if (pll_index[die] >= 4) log_error("Used more than available PLLs.\n"); if (ci.getPort(id_CLK_REF) == nullptr && ci.getPort(id_USR_CLK_REF) == nullptr) @@ -393,6 +384,14 @@ void GateMatePacker::pack_pll() if (ci.getPort(id_CLK_REF) != nullptr && ci.getPort(id_USR_CLK_REF) != nullptr) log_error("CLK_REF and USR_CLK_REF are not allowed to be set in same time.\n"); + ci.cluster = ci.name; + ci.constr_abs_z = true; + ci.constr_z = 2 + pll_index[die]; // Position to a proper Z location + + Loc fixed_loc = uarch->locations[std::make_pair(ctx->idf("PLL%d", pll_index[die]), die)]; + BelId pll_bel = ctx->getBelByLocation(fixed_loc); + ctx->bindBel(pll_bel, &ci, PlaceStrength::STRENGTH_FIXED); + clk = ci.getPort(id_CLK_REF); delay_t period = ctx->getDelayFromNS(1.0e9 / ctx->setting("target_freq")); if (clk) {