diff --git a/himbaechel/uarch/gatemate/bitstream.cc b/himbaechel/uarch/gatemate/bitstream.cc index 08ba82a6..b97c326f 100644 --- a/himbaechel/uarch/gatemate/bitstream.cc +++ b/himbaechel/uarch/gatemate/bitstream.cc @@ -252,13 +252,12 @@ struct BitstreamBackend case id_CPE_FF.index: case id_CPE_RAMI.index: case id_CPE_RAMO.index: - case id_CPE_RAMIO.index: - { + case id_CPE_RAMIO.index: { // Update configuration bits based on signal inversion dict params = cell.second->params; Loc l = ctx->getBelLocation(cell.second->bel); if (cell.second->type.in(id_CPE_L2T4, id_CPE_CI)) { - if (l.z==0) { + if (l.z == 0) { update_cpe_lt(cell.second.get(), id_IN1, id_INIT_L00, params); update_cpe_lt(cell.second.get(), id_IN2, id_INIT_L00, params); update_cpe_lt(cell.second.get(), id_IN3, id_INIT_L01, params); @@ -271,8 +270,8 @@ struct BitstreamBackend update_cpe_lt(cell.second.get(), id_IN4, id_INIT_L01, params); } } - if (l.z==7) { - if (cell.second->type.in(id_CPE_MX4)) { + if (l.z == 7) { + if (cell.second->type.in(id_CPE_MX4)) { update_cpe_mux(cell.second.get(), id_IN1, id_INIT_L11, 0, params); update_cpe_mux(cell.second.get(), id_IN2, id_INIT_L11, 1, params); update_cpe_mux(cell.second.get(), id_IN3, id_INIT_L11, 2, params); @@ -281,7 +280,7 @@ struct BitstreamBackend update_cpe_lt(cell.second.get(), id_IN6, id_INIT_L02, params); update_cpe_lt(cell.second.get(), id_IN7, id_INIT_L03, params); update_cpe_lt(cell.second.get(), id_IN8, id_INIT_L03, params); - } else { + } else { update_cpe_lt(cell.second.get(), id_IN1, id_INIT_L00, params); update_cpe_lt(cell.second.get(), id_IN2, id_INIT_L00, params); update_cpe_lt(cell.second.get(), id_IN3, id_INIT_L01, params); @@ -305,26 +304,40 @@ struct BitstreamBackend int id = tile_extra_data(cell.second.get()->bel.tile)->prim_id; for (auto &p : params) { IdString name = p.first; - switch(l.z) { - case 1 : // CPE_LT_L - switch(p.first.index) { - case id_INIT_L00.index : name = id_INIT_L02; break; - case id_INIT_L01.index : name = id_INIT_L03; break; - case id_INIT_L10.index : name = id_INIT_L11; break; - } + switch (l.z) { + case 1: // CPE_LT_L + switch (p.first.index) { + case id_INIT_L00.index: + name = id_INIT_L02; break; - case 4 : // CPE_RAMIO_U - switch(p.first.index) { - case id_C_RAM_I.index : name = id_C_RAM_I2; break; - case id_C_RAM_O.index : name = id_C_RAM_O2; break; - } + case id_INIT_L01.index: + name = id_INIT_L03; break; - case 5 : // CPE_RAMIO_L - switch(p.first.index) { - case id_C_RAM_I.index : name = id_C_RAM_I1; break; - case id_C_RAM_O.index : name = id_C_RAM_O1; break; - } + case id_INIT_L10.index: + name = id_INIT_L11; break; + } + break; + case 4: // CPE_RAMIO_U + switch (p.first.index) { + case id_C_RAM_I.index: + name = id_C_RAM_I2; + break; + case id_C_RAM_O.index: + name = id_C_RAM_O2; + break; + } + break; + case 5: // CPE_RAMIO_L + switch (p.first.index) { + case id_C_RAM_I.index: + name = id_C_RAM_I1; + break; + case id_C_RAM_O.index: + name = id_C_RAM_O1; + break; + } + break; } cc.tiles[loc].add_word(stringf("CPE%d.%s", id, name.c_str(ctx)), p.second.as_bits()); } diff --git a/himbaechel/uarch/gatemate/cells.cc b/himbaechel/uarch/gatemate/cells.cc index 98f743b4..93ea085f 100644 --- a/himbaechel/uarch/gatemate/cells.cc +++ b/himbaechel/uarch/gatemate/cells.cc @@ -33,7 +33,8 @@ CellInfo *GateMatePacker::create_cell_ptr(IdString type, IdString name) cell->ports[id].name = id; cell->ports[id].type = dir; }; - if (type.in(id_CPE_LT, id_CPE_LT_U, id_CPE_LT_L, id_CPE_L2T4, id_CPE_L2T5_U, id_CPE_L2T5_L, id_CPE_CI, id_CPE_DUMMY)) { + if (type.in(id_CPE_LT, id_CPE_LT_U, id_CPE_LT_L, id_CPE_L2T4, id_CPE_L2T5_U, id_CPE_L2T5_L, id_CPE_CI, + id_CPE_DUMMY)) { add_port(id_IN1, PORT_IN); add_port(id_IN2, PORT_IN); add_port(id_IN3, PORT_IN); diff --git a/himbaechel/uarch/gatemate/gatemate.cc b/himbaechel/uarch/gatemate/gatemate.cc index 8ce9902c..1a244611 100644 --- a/himbaechel/uarch/gatemate/gatemate.cc +++ b/himbaechel/uarch/gatemate/gatemate.cc @@ -194,14 +194,13 @@ void GateMateImpl::postPlace() ctx->assignArchInfo(); std::vector delete_cells; for (auto &cell : ctx->cells) { - if (cell.second->type.in(id_CPE_L2T4,id_CPE_CI)) { + if (cell.second->type.in(id_CPE_L2T4, id_CPE_CI)) { Loc l = ctx->getBelLocation(cell.second->bel); if (l.z == 1) { // CPE_HALF_L if (!cell.second->params.count(id_INIT_L20)) cell.second->params[id_INIT_L20] = Property(0b1100, 4); } - } - else if (cell.second->type.in(id_CPE_L2T5_L,id_CPE_LT_L)) { + } else if (cell.second->type.in(id_CPE_L2T5_L, id_CPE_LT_L)) { BelId bel = cell.second->bel; PlaceStrength strength = cell.second->belStrength; uint8_t func = int_or_default(cell.second->params, id_C_FUNCTION, 0); @@ -225,15 +224,29 @@ void GateMateImpl::postPlace() if (is_l2t5) { cell.second->type = id_CPE_L2T5; } else { - switch(func) { - case C_ADDF : cell.second->type = id_CPE_ADDF; break; - case C_ADDF2 : cell.second->type = id_CPE_ADDF2; break; - case C_MULT : cell.second->type = id_CPE_MULT; break; - case C_MX4 : cell.second->type = id_CPE_MX4; break; - case C_EN_CIN : cell.second->type = id_CPE_EN_CIN; break; - case C_CONCAT : cell.second->type = id_CPE_CONCAT; break; - case C_ADDCIN : cell.second->type = id_CPE_ADDCIN; break; - default: + switch (func) { + case C_ADDF: + cell.second->type = id_CPE_ADDF; + break; + case C_ADDF2: + cell.second->type = id_CPE_ADDF2; + break; + case C_MULT: + cell.second->type = id_CPE_MULT; + break; + case C_MX4: + cell.second->type = id_CPE_MX4; + break; + case C_EN_CIN: + cell.second->type = id_CPE_EN_CIN; + break; + case C_CONCAT: + cell.second->type = id_CPE_CONCAT; + break; + case C_ADDCIN: + cell.second->type = id_CPE_ADDCIN; + break; + default: break; } } @@ -255,7 +268,7 @@ void GateMateImpl::postPlace() } // Mark for deletion - else if (cell.second->type.in(id_CPE_L2T5_U,id_CPE_LT_U, id_CPE_DUMMY)) { + else if (cell.second->type.in(id_CPE_L2T5_U, id_CPE_LT_U, id_CPE_DUMMY)) { delete_cells.push_back(cell.second->name); } } @@ -360,7 +373,7 @@ bool GateMateImpl::isValidBelForCellType(IdString cell_type, BelId bel) const return cell_type.in(id_CPE_FF_U, id_CPE_FF); else if (bel_type == id_CPE_FF_L) return cell_type.in(id_CPE_FF_L, id_CPE_FF); - else if (bel_type.in(id_CPE_RAMIO_U,id_CPE_RAMIO_L)) + else if (bel_type.in(id_CPE_RAMIO_U, id_CPE_RAMIO_L)) return cell_type.in(id_CPE_RAMIO, id_CPE_RAMI, id_CPE_RAMO); else return (bel_type == cell_type); diff --git a/himbaechel/uarch/gatemate/pack.cc b/himbaechel/uarch/gatemate/pack.cc index 66b864b5..e5f65e3e 100644 --- a/himbaechel/uarch/gatemate/pack.cc +++ b/himbaechel/uarch/gatemate/pack.cc @@ -47,7 +47,7 @@ void GateMatePacker::disconnect_if_gnd(CellInfo *cell, IdString input) } } -std::pair GateMatePacker::move_ram_i(CellInfo *cell, IdString origPort, bool place, Loc cpe_loc) +std::pair GateMatePacker::move_ram_i(CellInfo *cell, IdString origPort, bool place, Loc cpe_loc) { CellInfo *cpe_half = nullptr; CellInfo *cpe_ramio = nullptr; @@ -63,7 +63,8 @@ std::pair GateMatePacker::move_ram_i(CellInfo *cell, IdStri BelId b = ctx->getBelByLocation(cpe_loc); ctx->bindBel(b, cpe_ramio, PlaceStrength::STRENGTH_FIXED); } - CellInfo * cpe_half = create_cell_ptr(id_CPE_DUMMY, ctx->idf("%s$%s_cpe", cell->name.c_str(ctx), origPort.c_str(ctx))); + CellInfo *cpe_half = + create_cell_ptr(id_CPE_DUMMY, ctx->idf("%s$%s_cpe", cell->name.c_str(ctx), origPort.c_str(ctx))); if (place) { cpe_ramio->constr_children.push_back(cpe_half); cpe_half->cluster = cell->cluster; @@ -84,7 +85,7 @@ std::pair GateMatePacker::move_ram_i(CellInfo *cell, IdStri return std::make_pair(cpe_half, cpe_ramio); } -std::pair GateMatePacker::move_ram_o(CellInfo *cell, IdString origPort, bool place, Loc cpe_loc) +std::pair GateMatePacker::move_ram_o(CellInfo *cell, IdString origPort, bool place, Loc cpe_loc) { CellInfo *cpe_half = nullptr; CellInfo *cpe_ramio = nullptr; @@ -134,14 +135,16 @@ std::pair GateMatePacker::move_ram_o(CellInfo *cell, IdStri return std::make_pair(cpe_half, cpe_ramio); } -std::pair GateMatePacker::move_ram_io(CellInfo *cell, IdString iPort, IdString oPort, bool place, Loc cpe_loc) +std::pair GateMatePacker::move_ram_io(CellInfo *cell, IdString iPort, IdString oPort, + bool place, Loc cpe_loc) { NetInfo *i_net = cell->getPort(iPort); NetInfo *o_net = cell->getPort(oPort); if (!i_net && !o_net) return std::make_pair(nullptr, nullptr); - CellInfo *cpe_ramio = create_cell_ptr(id_CPE_RAMIO, ctx->idf("%s$%s_ramio", cell->name.c_str(ctx), oPort.c_str(ctx))); + CellInfo *cpe_ramio = + create_cell_ptr(id_CPE_RAMIO, ctx->idf("%s$%s_ramio", cell->name.c_str(ctx), oPort.c_str(ctx))); if (place) { cell->constr_children.push_back(cpe_ramio); cpe_ramio->cluster = cell->cluster; @@ -195,17 +198,18 @@ std::pair GateMatePacker::move_ram_io(CellInfo *cell, IdStr return std::make_pair(cpe_half, cpe_ramio); } -std::pair GateMatePacker::move_ram_i_fixed(CellInfo *cell, IdString origPort, Loc fixed) +std::pair GateMatePacker::move_ram_i_fixed(CellInfo *cell, IdString origPort, Loc fixed) { return move_ram_i(cell, origPort, false, uarch->getRelativeConstraint(fixed, origPort)); } -std::pair GateMatePacker::move_ram_o_fixed(CellInfo *cell, IdString origPort, Loc fixed) +std::pair GateMatePacker::move_ram_o_fixed(CellInfo *cell, IdString origPort, Loc fixed) { return move_ram_o(cell, origPort, false, uarch->getRelativeConstraint(fixed, origPort)); } -std::pair GateMatePacker::move_ram_io_fixed(CellInfo *cell, IdString iPort, IdString oPort, Loc fixed) +std::pair GateMatePacker::move_ram_io_fixed(CellInfo *cell, IdString iPort, IdString oPort, + Loc fixed) { return move_ram_io(cell, iPort, oPort, false, uarch->getRelativeConstraint(fixed, oPort)); } diff --git a/himbaechel/uarch/gatemate/pack.h b/himbaechel/uarch/gatemate/pack.h index 96a22515..18d481f7 100644 --- a/himbaechel/uarch/gatemate/pack.h +++ b/himbaechel/uarch/gatemate/pack.h @@ -53,12 +53,15 @@ struct GateMatePacker PllCfgRecord get_pll_settings(double f_ref, double f_core, int mode, int low_jitter, bool pdiv0_mux, bool feedback); - std::pairmove_ram_i(CellInfo *cell, IdString origPort, bool place = true, Loc cpe_loc = Loc()); - std::pair move_ram_o(CellInfo *cell, IdString origPort, bool place = true, Loc cpe_loc = Loc()); - std::pair move_ram_io(CellInfo *cell, IdString iPort, IdString oPort, bool place = true, Loc cpe_loc = Loc()); - std::pair move_ram_i_fixed(CellInfo *cell, IdString origPort, Loc fixed); - std::pair move_ram_o_fixed(CellInfo *cell, IdString origPort, Loc fixed); - std::pair move_ram_io_fixed(CellInfo *cell, IdString iPort, IdString oPort, Loc fixed); + std::pair move_ram_i(CellInfo *cell, IdString origPort, bool place = true, + Loc cpe_loc = Loc()); + std::pair move_ram_o(CellInfo *cell, IdString origPort, bool place = true, + Loc cpe_loc = Loc()); + std::pair move_ram_io(CellInfo *cell, IdString iPort, IdString oPort, bool place = true, + Loc cpe_loc = Loc()); + std::pair move_ram_i_fixed(CellInfo *cell, IdString origPort, Loc fixed); + std::pair move_ram_o_fixed(CellInfo *cell, IdString origPort, Loc fixed); + std::pair move_ram_io_fixed(CellInfo *cell, IdString iPort, IdString oPort, Loc fixed); uint8_t ram_ctrl_signal(CellInfo *cell, IdString port, bool alt); uint8_t ram_clk_signal(CellInfo *cell, IdString port); bool is_gpio_valid_dff(CellInfo *dff); diff --git a/himbaechel/uarch/gatemate/pack_cpe.cc b/himbaechel/uarch/gatemate/pack_cpe.cc index 75823c5c..3b08cf33 100644 --- a/himbaechel/uarch/gatemate/pack_cpe.cc +++ b/himbaechel/uarch/gatemate/pack_cpe.cc @@ -192,7 +192,7 @@ void GateMatePacker::pack_cpe() dff->renamePort(id_D, id_DIN); dff->renamePort(id_Q, id_DOUT); dff_to_cpe(dff); - dff->type=id_CPE_FF; + dff->type = id_CPE_FF; } } } diff --git a/himbaechel/uarch/gatemate/pack_io.cc b/himbaechel/uarch/gatemate/pack_io.cc index 434aeb1a..92bf0117 100644 --- a/himbaechel/uarch/gatemate/pack_io.cc +++ b/himbaechel/uarch/gatemate/pack_io.cc @@ -480,7 +480,7 @@ void GateMatePacker::pack_io_sel() oddr->movePortTo(id_D1, &ci, id_OUT1); const auto &pad = ctx->get_package_pin(ctx->id(loc)); int die = uarch->tile_extra_data(ci.bel.tile)->die; - auto [cpe_half,cpe_ramio] = ddr[die][pad->pad_bank]; + auto [cpe_half, cpe_ramio] = ddr[die][pad->pad_bank]; if (cpe_half) { if (cpe_half->getPort(id_IN1) != oddr->getPort(id_DDR)) log_error("DDR port use signal different than already occupied DDR source.\n");