From 6715329a1dcb969377d6a3407b3d7525aec6472e Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Tue, 8 Jul 2025 10:06:04 +0200 Subject: [PATCH] Move ramio code to pack_cpe --- himbaechel/uarch/gatemate/pack.cc | 167 -------------------------- himbaechel/uarch/gatemate/pack_cpe.cc | 167 ++++++++++++++++++++++++++ 2 files changed, 167 insertions(+), 167 deletions(-) diff --git a/himbaechel/uarch/gatemate/pack.cc b/himbaechel/uarch/gatemate/pack.cc index 37f1e811..24fa57ec 100644 --- a/himbaechel/uarch/gatemate/pack.cc +++ b/himbaechel/uarch/gatemate/pack.cc @@ -49,173 +49,6 @@ void GateMatePacker::disconnect_if_gnd(CellInfo *cell, IdString input) } } -std::pair GateMatePacker::move_ram_i(CellInfo *cell, IdString origPort, bool place, Loc cpe_loc) -{ - CellInfo *cpe_half = nullptr; - CellInfo *cpe_ramio = nullptr; - NetInfo *net = cell->getPort(origPort); - if (net) { - cpe_ramio = create_cell_ptr(id_CPE_RAMI, ctx->idf("%s$%s_rami", cell->name.c_str(ctx), origPort.c_str(ctx))); - if (place) { - cell->constr_children.push_back(cpe_ramio); - cpe_ramio->cluster = cell->cluster; - cpe_ramio->constr_abs_z = false; - cpe_ramio->constr_z = PLACE_DB_CONSTR + origPort.index; - } else { - BelId b = ctx->getBelByLocation(cpe_loc); - ctx->bindBel(b, cpe_ramio, PlaceStrength::STRENGTH_FIXED); - } - CellInfo *cpe_half = - create_cell_ptr(id_CPE_DUMMY, ctx->idf("%s$%s_cpe", cell->name.c_str(ctx), origPort.c_str(ctx))); - if (place) { - cpe_ramio->constr_children.push_back(cpe_half); - cpe_half->cluster = cell->cluster; - cpe_half->constr_abs_z = false; - cpe_half->constr_z = -4; - } else { - BelId b = ctx->getBelByLocation(Loc(cpe_loc.x, cpe_loc.y, cpe_loc.z - 4)); - ctx->bindBel(b, cpe_half, PlaceStrength::STRENGTH_FIXED); - } - - cpe_ramio->params[id_C_RAM_I] = Property(1, 1); - - NetInfo *ram_i = ctx->createNet(ctx->idf("%s$ram_i", cpe_ramio->name.c_str(ctx))); - cell->movePortTo(origPort, cpe_ramio, id_OUT); - cell->connectPort(origPort, ram_i); - cpe_ramio->connectPort(id_RAM_I, ram_i); - } - return std::make_pair(cpe_half, cpe_ramio); -} - -std::pair GateMatePacker::move_ram_o(CellInfo *cell, IdString origPort, bool place, Loc cpe_loc) -{ - CellInfo *cpe_half = nullptr; - CellInfo *cpe_ramio = nullptr; - NetInfo *net = cell->getPort(origPort); - if (net) { - cpe_ramio = create_cell_ptr(id_CPE_RAMO, ctx->idf("%s$%s_ramo", cell->name.c_str(ctx), origPort.c_str(ctx))); - if (place) { - cell->constr_children.push_back(cpe_ramio); - cpe_ramio->cluster = cell->cluster; - cpe_ramio->constr_abs_z = false; - cpe_ramio->constr_z = PLACE_DB_CONSTR + origPort.index; - } else { - BelId b = ctx->getBelByLocation(cpe_loc); - ctx->bindBel(b, cpe_ramio, PlaceStrength::STRENGTH_FIXED); - } - cpe_half = create_cell_ptr(id_CPE_L2T4, ctx->idf("%s$%s_cpe", cell->name.c_str(ctx), origPort.c_str(ctx))); - if (place) { - cpe_ramio->constr_children.push_back(cpe_half); - cpe_half->cluster = cell->cluster; - cpe_half->constr_abs_z = false; - cpe_half->constr_z = -4; - } else { - BelId b = ctx->getBelByLocation(Loc(cpe_loc.x, cpe_loc.y, cpe_loc.z - 4)); - ctx->bindBel(b, cpe_half, PlaceStrength::STRENGTH_FIXED); - } - if (net->name == ctx->id("$PACKER_GND")) { - cpe_half->params[id_INIT_L00] = Property(LUT_ZERO, 4); - cell->disconnectPort(origPort); - } else if (net->name == ctx->id("$PACKER_VCC")) { - cpe_half->params[id_INIT_L00] = Property(LUT_ONE, 4); - cell->disconnectPort(origPort); - } else { - cpe_half->params[id_INIT_L00] = Property(LUT_D0, 4); - cell->movePortTo(origPort, cpe_half, id_IN1); - } - cpe_half->params[id_INIT_L10] = Property(LUT_D0, 4); - - cpe_ramio->params[id_C_RAM_O] = Property(1, 1); - NetInfo *ram_o = ctx->createNet(ctx->idf("%s$ram_o", cpe_half->name.c_str(ctx))); - cell->connectPort(origPort, ram_o); - cpe_ramio->connectPort(id_RAM_O, ram_o); - - NetInfo *out = ctx->createNet(ctx->idf("%s$out", cpe_half->name.c_str(ctx))); - cpe_half->connectPort(id_OUT, out); - cpe_ramio->connectPort(id_I, out); - } - return std::make_pair(cpe_half, cpe_ramio); -} - -std::pair GateMatePacker::move_ram_io(CellInfo *cell, IdString iPort, IdString oPort, - bool place, Loc cpe_loc) -{ - NetInfo *i_net = cell->getPort(iPort); - NetInfo *o_net = cell->getPort(oPort); - if (!i_net && !o_net) - return std::make_pair(nullptr, nullptr); - - CellInfo *cpe_ramio = - create_cell_ptr(id_CPE_RAMIO, ctx->idf("%s$%s_ramio", cell->name.c_str(ctx), oPort.c_str(ctx))); - if (place) { - cell->constr_children.push_back(cpe_ramio); - cpe_ramio->cluster = cell->cluster; - cpe_ramio->constr_abs_z = false; - cpe_ramio->constr_z = PLACE_DB_CONSTR + oPort.index; - } else { - BelId b = ctx->getBelByLocation(cpe_loc); - ctx->bindBel(b, cpe_ramio, PlaceStrength::STRENGTH_FIXED); - } - CellInfo *cpe_half = create_cell_ptr(id_CPE_L2T4, ctx->idf("%s$%s_cpe", cell->name.c_str(ctx), oPort.c_str(ctx))); - if (place) { - cpe_ramio->constr_children.push_back(cpe_half); - cpe_half->cluster = cell->cluster; - cpe_half->constr_abs_z = false; - cpe_half->constr_z = -4; - } else { - BelId b = ctx->getBelByLocation(Loc(cpe_loc.x, cpe_loc.y, cpe_loc.z - 4)); - ctx->bindBel(b, cpe_half, PlaceStrength::STRENGTH_FIXED); - } - - if (o_net) { - if (o_net->name == ctx->id("$PACKER_GND")) { - cpe_half->params[id_INIT_L00] = Property(LUT_ZERO, 4); - cell->disconnectPort(oPort); - } else if (o_net->name == ctx->id("$PACKER_VCC")) { - cpe_half->params[id_INIT_L00] = Property(LUT_ONE, 4); - cell->disconnectPort(oPort); - } else { - cpe_half->params[id_INIT_L00] = Property(LUT_D0, 4); - cell->movePortTo(oPort, cpe_half, id_IN1); - } - cpe_half->params[id_INIT_L10] = Property(LUT_D0, 4); - cpe_ramio->params[id_C_RAM_O] = Property(1, 1); - - NetInfo *ram_o = ctx->createNet(ctx->idf("%s$ram_o", cpe_half->name.c_str(ctx))); - cell->connectPort(oPort, ram_o); - cpe_ramio->connectPort(id_RAM_O, ram_o); - - NetInfo *out = ctx->createNet(ctx->idf("%s$out", cpe_half->name.c_str(ctx))); - cpe_half->connectPort(id_OUT, out); - cpe_ramio->connectPort(id_I, out); - } - if (i_net) { - cpe_ramio->params[id_C_RAM_I] = Property(1, 1); - - NetInfo *ram_i = ctx->createNet(ctx->idf("%s$ram_i", cpe_half->name.c_str(ctx))); - cell->movePortTo(iPort, cpe_ramio, id_OUT); - cell->connectPort(iPort, ram_i); - cpe_ramio->connectPort(id_RAM_I, ram_i); - } - return std::make_pair(cpe_half, cpe_ramio); -} - -std::pair GateMatePacker::move_ram_i_fixed(CellInfo *cell, IdString origPort, Loc fixed) -{ - return move_ram_i(cell, origPort, false, uarch->getRelativeConstraint(fixed, origPort)); -} - -std::pair GateMatePacker::move_ram_o_fixed(CellInfo *cell, IdString origPort, Loc fixed) -{ - return move_ram_o(cell, origPort, false, uarch->getRelativeConstraint(fixed, origPort)); -} - -std::pair GateMatePacker::move_ram_io_fixed(CellInfo *cell, IdString iPort, IdString oPort, - Loc fixed) -{ - return move_ram_io(cell, iPort, oPort, false, uarch->getRelativeConstraint(fixed, oPort)); -} - void GateMatePacker::pack_misc() { for (auto &cell : ctx->cells) { diff --git a/himbaechel/uarch/gatemate/pack_cpe.cc b/himbaechel/uarch/gatemate/pack_cpe.cc index 0c93c0b6..5ceb00ea 100644 --- a/himbaechel/uarch/gatemate/pack_cpe.cc +++ b/himbaechel/uarch/gatemate/pack_cpe.cc @@ -645,4 +645,171 @@ void GateMatePacker::remove_constants() } } +std::pair GateMatePacker::move_ram_i(CellInfo *cell, IdString origPort, bool place, Loc cpe_loc) +{ + CellInfo *cpe_half = nullptr; + CellInfo *cpe_ramio = nullptr; + NetInfo *net = cell->getPort(origPort); + if (net) { + cpe_ramio = create_cell_ptr(id_CPE_RAMI, ctx->idf("%s$%s_rami", cell->name.c_str(ctx), origPort.c_str(ctx))); + if (place) { + cell->constr_children.push_back(cpe_ramio); + cpe_ramio->cluster = cell->cluster; + cpe_ramio->constr_abs_z = false; + cpe_ramio->constr_z = PLACE_DB_CONSTR + origPort.index; + } else { + BelId b = ctx->getBelByLocation(cpe_loc); + ctx->bindBel(b, cpe_ramio, PlaceStrength::STRENGTH_FIXED); + } + CellInfo *cpe_half = + create_cell_ptr(id_CPE_DUMMY, ctx->idf("%s$%s_cpe", cell->name.c_str(ctx), origPort.c_str(ctx))); + if (place) { + cpe_ramio->constr_children.push_back(cpe_half); + cpe_half->cluster = cell->cluster; + cpe_half->constr_abs_z = false; + cpe_half->constr_z = -4; + } else { + BelId b = ctx->getBelByLocation(Loc(cpe_loc.x, cpe_loc.y, cpe_loc.z - 4)); + ctx->bindBel(b, cpe_half, PlaceStrength::STRENGTH_FIXED); + } + + cpe_ramio->params[id_C_RAM_I] = Property(1, 1); + + NetInfo *ram_i = ctx->createNet(ctx->idf("%s$ram_i", cpe_ramio->name.c_str(ctx))); + cell->movePortTo(origPort, cpe_ramio, id_OUT); + cell->connectPort(origPort, ram_i); + cpe_ramio->connectPort(id_RAM_I, ram_i); + } + return std::make_pair(cpe_half, cpe_ramio); +} + +std::pair GateMatePacker::move_ram_o(CellInfo *cell, IdString origPort, bool place, Loc cpe_loc) +{ + CellInfo *cpe_half = nullptr; + CellInfo *cpe_ramio = nullptr; + NetInfo *net = cell->getPort(origPort); + if (net) { + cpe_ramio = create_cell_ptr(id_CPE_RAMO, ctx->idf("%s$%s_ramo", cell->name.c_str(ctx), origPort.c_str(ctx))); + if (place) { + cell->constr_children.push_back(cpe_ramio); + cpe_ramio->cluster = cell->cluster; + cpe_ramio->constr_abs_z = false; + cpe_ramio->constr_z = PLACE_DB_CONSTR + origPort.index; + } else { + BelId b = ctx->getBelByLocation(cpe_loc); + ctx->bindBel(b, cpe_ramio, PlaceStrength::STRENGTH_FIXED); + } + cpe_half = create_cell_ptr(id_CPE_L2T4, ctx->idf("%s$%s_cpe", cell->name.c_str(ctx), origPort.c_str(ctx))); + if (place) { + cpe_ramio->constr_children.push_back(cpe_half); + cpe_half->cluster = cell->cluster; + cpe_half->constr_abs_z = false; + cpe_half->constr_z = -4; + } else { + BelId b = ctx->getBelByLocation(Loc(cpe_loc.x, cpe_loc.y, cpe_loc.z - 4)); + ctx->bindBel(b, cpe_half, PlaceStrength::STRENGTH_FIXED); + } + if (net->name == ctx->id("$PACKER_GND")) { + cpe_half->params[id_INIT_L00] = Property(LUT_ZERO, 4); + cell->disconnectPort(origPort); + } else if (net->name == ctx->id("$PACKER_VCC")) { + cpe_half->params[id_INIT_L00] = Property(LUT_ONE, 4); + cell->disconnectPort(origPort); + } else { + cpe_half->params[id_INIT_L00] = Property(LUT_D0, 4); + cell->movePortTo(origPort, cpe_half, id_IN1); + } + cpe_half->params[id_INIT_L10] = Property(LUT_D0, 4); + + cpe_ramio->params[id_C_RAM_O] = Property(1, 1); + NetInfo *ram_o = ctx->createNet(ctx->idf("%s$ram_o", cpe_half->name.c_str(ctx))); + cell->connectPort(origPort, ram_o); + cpe_ramio->connectPort(id_RAM_O, ram_o); + + NetInfo *out = ctx->createNet(ctx->idf("%s$out", cpe_half->name.c_str(ctx))); + cpe_half->connectPort(id_OUT, out); + cpe_ramio->connectPort(id_I, out); + } + return std::make_pair(cpe_half, cpe_ramio); +} + +std::pair GateMatePacker::move_ram_io(CellInfo *cell, IdString iPort, IdString oPort, + bool place, Loc cpe_loc) +{ + NetInfo *i_net = cell->getPort(iPort); + NetInfo *o_net = cell->getPort(oPort); + if (!i_net && !o_net) + return std::make_pair(nullptr, nullptr); + + CellInfo *cpe_ramio = + create_cell_ptr(id_CPE_RAMIO, ctx->idf("%s$%s_ramio", cell->name.c_str(ctx), oPort.c_str(ctx))); + if (place) { + cell->constr_children.push_back(cpe_ramio); + cpe_ramio->cluster = cell->cluster; + cpe_ramio->constr_abs_z = false; + cpe_ramio->constr_z = PLACE_DB_CONSTR + oPort.index; + } else { + BelId b = ctx->getBelByLocation(cpe_loc); + ctx->bindBel(b, cpe_ramio, PlaceStrength::STRENGTH_FIXED); + } + CellInfo *cpe_half = create_cell_ptr(id_CPE_L2T4, ctx->idf("%s$%s_cpe", cell->name.c_str(ctx), oPort.c_str(ctx))); + if (place) { + cpe_ramio->constr_children.push_back(cpe_half); + cpe_half->cluster = cell->cluster; + cpe_half->constr_abs_z = false; + cpe_half->constr_z = -4; + } else { + BelId b = ctx->getBelByLocation(Loc(cpe_loc.x, cpe_loc.y, cpe_loc.z - 4)); + ctx->bindBel(b, cpe_half, PlaceStrength::STRENGTH_FIXED); + } + + if (o_net) { + if (o_net->name == ctx->id("$PACKER_GND")) { + cpe_half->params[id_INIT_L00] = Property(LUT_ZERO, 4); + cell->disconnectPort(oPort); + } else if (o_net->name == ctx->id("$PACKER_VCC")) { + cpe_half->params[id_INIT_L00] = Property(LUT_ONE, 4); + cell->disconnectPort(oPort); + } else { + cpe_half->params[id_INIT_L00] = Property(LUT_D0, 4); + cell->movePortTo(oPort, cpe_half, id_IN1); + } + cpe_half->params[id_INIT_L10] = Property(LUT_D0, 4); + cpe_ramio->params[id_C_RAM_O] = Property(1, 1); + + NetInfo *ram_o = ctx->createNet(ctx->idf("%s$ram_o", cpe_half->name.c_str(ctx))); + cell->connectPort(oPort, ram_o); + cpe_ramio->connectPort(id_RAM_O, ram_o); + + NetInfo *out = ctx->createNet(ctx->idf("%s$out", cpe_half->name.c_str(ctx))); + cpe_half->connectPort(id_OUT, out); + cpe_ramio->connectPort(id_I, out); + } + if (i_net) { + cpe_ramio->params[id_C_RAM_I] = Property(1, 1); + + NetInfo *ram_i = ctx->createNet(ctx->idf("%s$ram_i", cpe_half->name.c_str(ctx))); + cell->movePortTo(iPort, cpe_ramio, id_OUT); + cell->connectPort(iPort, ram_i); + cpe_ramio->connectPort(id_RAM_I, ram_i); + } + return std::make_pair(cpe_half, cpe_ramio); +} + +std::pair GateMatePacker::move_ram_i_fixed(CellInfo *cell, IdString origPort, Loc fixed) +{ + return move_ram_i(cell, origPort, false, uarch->getRelativeConstraint(fixed, origPort)); +} + +std::pair GateMatePacker::move_ram_o_fixed(CellInfo *cell, IdString origPort, Loc fixed) +{ + return move_ram_o(cell, origPort, false, uarch->getRelativeConstraint(fixed, origPort)); +} + +std::pair GateMatePacker::move_ram_io_fixed(CellInfo *cell, IdString iPort, IdString oPort, + Loc fixed) +{ + return move_ram_io(cell, iPort, oPort, false, uarch->getRelativeConstraint(fixed, oPort)); +} + NEXTPNR_NAMESPACE_END