From 4e9debe4e5f7eed9463dbda77d1fb4e57be87cfe Mon Sep 17 00:00:00 2001 From: gatecat Date: Wed, 15 Apr 2026 09:24:33 +0200 Subject: [PATCH] ecp5: Fix timing for DCU clock outputs Signed-off-by: gatecat --- ecp5/arch.cc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/ecp5/arch.cc b/ecp5/arch.cc index 3a854027..55a5346e 100644 --- a/ecp5/arch.cc +++ b/ecp5/arch.cc @@ -1015,6 +1015,8 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, in } else if (cell->type.in(id_DCUA, id_EXTREFB, id_PCSCLKDIV)) { if (port.in(id_CH0_FF_TXI_CLK, id_CH0_FF_RXI_CLK, id_CH1_FF_TXI_CLK, id_CH1_FF_RXI_CLK)) return TMG_CLOCK_INPUT; + if (port.in(id_CH0_FF_TX_PCLK, id_CH0_FF_RX_PCLK, id_CH1_FF_TX_PCLK, id_CH1_FF_RX_PCLK)) + return TMG_GEN_CLOCK; std::string prefix = port.str(this).substr(0, 9); if (prefix == "CH0_FF_TX" || prefix == "CH0_FF_RX" || prefix == "CH1_FF_TX" || prefix == "CH1_FF_RX") { clockInfoCount = 1;