From 4cefb7ea87b9bcc8ca323fa5f23eddcedcceaec1 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Tue, 1 Jul 2025 13:09:42 +0200 Subject: [PATCH] Cleanup for adders --- himbaechel/uarch/gatemate/bitstream.cc | 3 +-- himbaechel/uarch/gatemate/cells.cc | 4 ++-- himbaechel/uarch/gatemate/constids.inc | 1 - himbaechel/uarch/gatemate/gatemate.cc | 6 +++--- himbaechel/uarch/gatemate/pack_cpe.cc | 22 ++++++++++++++++------ 5 files changed, 22 insertions(+), 14 deletions(-) diff --git a/himbaechel/uarch/gatemate/bitstream.cc b/himbaechel/uarch/gatemate/bitstream.cc index 5ee54f5d..d5927b66 100644 --- a/himbaechel/uarch/gatemate/bitstream.cc +++ b/himbaechel/uarch/gatemate/bitstream.cc @@ -277,7 +277,6 @@ struct BitstreamBackend case id_CPE_EN_CIN.index: case id_CPE_CONCAT.index: case id_CPE_ADDCIN.index: - case id_CPE_CI.index: case id_CPE_FF.index: case id_CPE_LATCH.index: case id_CPE_RAMI.index: @@ -286,7 +285,7 @@ struct BitstreamBackend // Update configuration bits based on signal inversion dict params = cell.second->params; Loc l = ctx->getBelLocation(cell.second->bel); - if (cell.second->type.in(id_CPE_L2T4, id_CPE_CI, id_CPE_LT_L, id_CPE_LT_U)) { + if (cell.second->type.in(id_CPE_L2T4, id_CPE_LT_L, id_CPE_LT_U)) { if (l.z == CPE_LT_U_Z) { update_cpe_lt(cell.second.get(), id_IN1, id_INIT_L00, params); update_cpe_lt(cell.second.get(), id_IN2, id_INIT_L00, params); diff --git a/himbaechel/uarch/gatemate/cells.cc b/himbaechel/uarch/gatemate/cells.cc index 5daf7116..045dc6b6 100644 --- a/himbaechel/uarch/gatemate/cells.cc +++ b/himbaechel/uarch/gatemate/cells.cc @@ -33,14 +33,14 @@ CellInfo *GateMatePacker::create_cell_ptr(IdString type, IdString name) cell->ports[id].name = id; cell->ports[id].type = dir; }; - if (type.in(id_CPE_LT, id_CPE_LT_U, id_CPE_LT_L, id_CPE_L2T4, id_CPE_L2T5_U, id_CPE_L2T5_L, id_CPE_CI, + if (type.in(id_CPE_LT, id_CPE_LT_U, id_CPE_LT_L, id_CPE_L2T4, id_CPE_L2T5_U, id_CPE_L2T5_L, id_CPE_DUMMY)) { add_port(id_IN1, PORT_IN); add_port(id_IN2, PORT_IN); add_port(id_IN3, PORT_IN); add_port(id_IN4, PORT_IN); add_port(id_OUT, PORT_OUT); - if (type.in(id_CPE_LT_L, id_CPE_L2T5_L, id_CPE_CI)) { + if (type.in(id_CPE_LT_L, id_CPE_L2T5_L)) { add_port(id_CINX, PORT_IN); add_port(id_PINX, PORT_IN); add_port(id_CINY1, PORT_IN); diff --git a/himbaechel/uarch/gatemate/constids.inc b/himbaechel/uarch/gatemate/constids.inc index 26fa847c..6e6f210b 100644 --- a/himbaechel/uarch/gatemate/constids.inc +++ b/himbaechel/uarch/gatemate/constids.inc @@ -2265,6 +2265,5 @@ X(CPE_MX4) X(CPE_EN_CIN) X(CPE_CONCAT) X(CPE_ADDCIN) -X(CPE_CI) X(CPE_DUMMY) X(CPE_LATCH) diff --git a/himbaechel/uarch/gatemate/gatemate.cc b/himbaechel/uarch/gatemate/gatemate.cc index f538db2d..16144d98 100644 --- a/himbaechel/uarch/gatemate/gatemate.cc +++ b/himbaechel/uarch/gatemate/gatemate.cc @@ -207,7 +207,7 @@ void GateMateImpl::postPlace() rename_param(cell.second.get(), id_INIT_L03, id_INIT_L01, 4); rename_param(cell.second.get(), id_INIT_L11, id_INIT_L10, 4); } - } else if (cell.second->type.in(id_CPE_L2T4, id_CPE_CI)) { + } else if (cell.second->type.in(id_CPE_L2T4)) { Loc l = ctx->getBelLocation(cell.second->bel); if (l.z == CPE_LT_L_Z) { if (!cell.second->params.count(id_INIT_L20)) @@ -350,7 +350,7 @@ IdString GateMateImpl::getBelBucketForCellType(IdString cell_type) const if (cell_type.in(id_CPE_IBUF, id_CPE_OBUF, id_CPE_TOBUF, id_CPE_IOBUF, id_CPE_LVDS_IBUF, id_CPE_LVDS_TOBUF, id_CPE_LVDS_OBUF, id_CPE_LVDS_IOBUF)) return id_GPIO; - else if (cell_type.in(id_CPE_LT_U, id_CPE_LT_L, id_CPE_LT, id_CPE_L2T4, id_CPE_L2T5_L, id_CPE_L2T5_U, id_CPE_CI)) + else if (cell_type.in(id_CPE_LT_U, id_CPE_LT_L, id_CPE_LT, id_CPE_L2T4, id_CPE_L2T5_L, id_CPE_L2T5_U)) return id_CPE_LT; else if (cell_type.in(id_CPE_FF_U, id_CPE_FF_L, id_CPE_FF, id_CPE_LATCH)) return id_CPE_FF; @@ -381,7 +381,7 @@ bool GateMateImpl::isValidBelForCellType(IdString cell_type, BelId bel) const else if (bel_type == id_CPE_LT_U) return cell_type.in(id_CPE_LT_U, id_CPE_LT, id_CPE_L2T4, id_CPE_L2T5_U, id_CPE_DUMMY); else if (bel_type == id_CPE_LT_L) - return cell_type.in(id_CPE_LT_L, id_CPE_LT, id_CPE_L2T4, id_CPE_L2T5_L, id_CPE_CI, id_CPE_DUMMY); + return cell_type.in(id_CPE_LT_L, id_CPE_LT, id_CPE_L2T4, id_CPE_L2T5_L, id_CPE_DUMMY); else if (bel_type == id_CPE_FF_U) return cell_type.in(id_CPE_FF_U, id_CPE_FF, id_CPE_LATCH); else if (bel_type == id_CPE_FF_L) diff --git a/himbaechel/uarch/gatemate/pack_cpe.cc b/himbaechel/uarch/gatemate/pack_cpe.cc index 3cc27195..913aa5cb 100644 --- a/himbaechel/uarch/gatemate/pack_cpe.cc +++ b/himbaechel/uarch/gatemate/pack_cpe.cc @@ -399,17 +399,27 @@ void GateMatePacker::pack_addf() ci_upper->constr_z = -1; ci_upper->constr_y = -1; - CellInfo *ci_lower = create_cell_ptr(id_CPE_CI, ctx->idf("%s$ci", root->name.c_str(ctx))); + CellInfo *ci_lower = create_cell_ptr(id_CPE_L2T4, ctx->idf("%s$ci", root->name.c_str(ctx))); root->constr_children.push_back(ci_lower); ci_lower->cluster = root->name; ci_lower->constr_abs_z = false; ci_lower->constr_y = -1; - // TODO: Maybe move this to bitstream gen - ci_lower->params[id_C_O1] = Property(0b11, 2); - ci_lower->params[id_C_SELY1] = Property(1, 1); - ci_lower->params[id_C_CY1_I] = Property(1, 1); + ci_lower->params[id_INIT_L00] = Property(0b0000, 4); // zero ci_lower->params[id_INIT_L10] = Property(0b1010, 4); // D0 + CellInfo *ci_cplines = create_cell_ptr(id_CPE_CPLINES, ctx->idf("%s$ci_cplines", root->name.c_str(ctx))); + ci_cplines->params[id_C_SELY1] = Property(1, 1); + ci_cplines->params[id_C_CY1_I] = Property(1, 1); + root->constr_children.push_back(ci_cplines); + ci_cplines->cluster = root->name; + ci_cplines->constr_abs_z = true; + ci_cplines->constr_y = -1; + ci_cplines->constr_z = CPE_CPLINES_Z; + NetInfo *ci_out_conn = ctx->createNet(ctx->idf("%s$out", ci_lower->name.c_str(ctx))); + ci_lower->connectPort(id_OUT, ci_out_conn); + ci_cplines->connectPort(id_OUT1, ci_out_conn); + + NetInfo *ci_net = root->getPort(id_CI); if (ci_net->name == ctx->id("$PACKER_GND")) { ci_lower->params[id_INIT_L00] = Property(0b0000, 4); @@ -423,7 +433,7 @@ void GateMatePacker::pack_addf() } NetInfo *ci_conn = ctx->createNet(ctx->idf("%s$ci_net", root->name.c_str(ctx))); - ci_lower->connectPort(id_COUTY1, ci_conn); + ci_cplines->connectPort(id_COUTY1, ci_conn); root->ports[id_CINY1].name = id_CINY1; root->ports[id_CINY1].type = PORT_IN;